TIGUAN: Thread-parallel integrated test pattern generator utilizing satisfiability analysis

Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

Volumn , Issue , 2009, Pages 227-232

  Czutro, Alejandro ^a   Ilia, Polian ^a   Lewis, Matthew ^a   Engelke, Piet ^a   Reddy, Sudhakar M ^b   Becker, Bernd ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

AUTOMATIC TEST PATTERN GENERATORS; FAULT MODELS; INDUSTRIAL CIRCUITS; OPTIMIZATION TECHNIQUES; SAT SOLVERS; SATISFIABILITY; STUCK-AT FAULTS; TEST PATTERN GENERATORS;

EMBEDDED SYSTEMS;

EID: 62949113749     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2009.20     Document Type: Conference Paper

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