Fault diagnosis and logic debugging using Boolean satisfiability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 10, 2005, Pages 1606-1620

  Smith, Alexander ^a,b   Veneris, Andreas ^a,b,d,e,f,g   Fahim Ali, Moayad ^a,b   Viglas, Anastasios ^a,c,h  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c UNIVERSITY OF SYDNEY   (Australia)

^d Department of Electrical and Computer Engineering ^*  (United States)

^e ACM   (Canada)

^f TECHNICAL CHAMBER OF GREECE   (Greece)

^g Planetary Society   (United States)

^h ACM   (Australia)

Author keywords

Boolean satisfiability debugging; Design errors; Diagnosis; Faults; Verification; VLSI

Indexed keywords

BOOLEAN SATISFIABILITY DEBUGGING; DESIGN ERRORS; FAULT DIAGNOSIS; VERIFICATION;

DATA STORAGE EQUIPMENT; ERROR ANALYSIS; FORMAL LOGIC; HEURISTIC METHODS; PROBLEM SOLVING; VLSI CIRCUITS;

PROGRAM DEBUGGING;

EID: 27144460537     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.852031     Document Type: Article

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