A Basis for formal robustness checking

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 784-789

  Fey, Görschwin ^a,b   Drechsler, Rolf ^b  

^a UNIVERSITY OF TOKYO   (Japan)

^b UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS ENGINEERING;

EFFICIENT METHODS; ELECTRONIC DESIGNS; INPUT/OUTPUT; INTERNATIONAL SYMPOSIUM; PROPERTY CHECKING; SEQUENTIAL EQUIVALENCE CHECKING;

NETWORKS (CIRCUITS);

EID: 49749104886     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479838     Document Type: Conference Paper

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