In-place FPGA retiming for mitigation of variational single-event transient faults

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 58, Issue 6, 2011, Pages 1372-1381

  Xu, Wenyao ^a   Wang, Jia ^b   Hu, Yu ^c   Lee, Ju Yueh ^a   Gong, Fang ^a   He, Lei ^a   Sarrafzadeh, Majid ^a  

^a Department of Civil and Environmental Engineering   (United States)

^b Illinois Institute of Technology   (United States)

^c UNIVERSITY OF ALBERTA   (Canada)

Author keywords

Field programmable gate arrays (FPGAs); retiming; single event transients

Indexed keywords

COMPUTER CONTROL SYSTEMS; FLASH MEMORY; FLIP FLOP CIRCUITS; INDUCTIVE LOGIC PROGRAMMING (ILP); INTEGER PROGRAMMING; LOGIC GATES; RADIATION HARDENING; TIME-TO-FAILURE; TRANSIENTS;

COMBINATIONAL PATHS; FPGA ARCHITECTURES; INTEGER LINEAR PROGRAMMING; MITIGATION TECHNIQUES; RETIMING; RETIMING ALGORITHMS; SINGLE EVENT TRANSIENTS; SINGLE EVENT UPSETS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79957967434     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2010.2094370     Document Type: Article

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