-
1
-
-
2642540033
-
Cache scrubbing in microprocessors: Myth or necessity?
-
Mar.
-
S. S. Mukherjee, J. Emer, T. Fossum, and S. K. Reinhardt, "Cache scrubbing in microprocessors: Myth or necessity?," in pROC. 10th IEEE Pacific Rim Int. Symp. Dependable Computing, Mar. 2004, pp. 37-42.
-
(2004)
PROC. 10th IEEE Pacific Rim Int. Symp. Dependable Computing
, pp. 37-42
-
-
Mukherjee, S.S.1
Emer, J.2
Fossum, T.3
Reinhardt, S.K.4
-
2
-
-
21644463896
-
Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology
-
Dec.
-
Y. Tosaka, H. Ehara, M. Igeta, T. Uemura, H. Oka, N. Matsuoka, and K. Hatanaka, "Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology," in Proc. IEDM, Dec. 2004, pp. 941-944.
-
(2004)
Proc. IEDM
, pp. 941-944
-
-
Tosaka, Y.1
Ehara, H.2
Igeta, M.3
Uemura, T.4
Oka, H.5
Matsuoka, N.6
Hatanaka, K.7
-
3
-
-
53849127858
-
Low power ternary content-addressable memories (TCAM) design using segmented match-line
-
Jul.
-
S. Baeg, "Low power ternary content-addressable memories (TCAM) design using segmented match-line," IEEE Trans. on CAS-I, vol.55, no.6, pp. 1485-1494, Jul. 2008.
-
(2008)
IEEE Trans. on CAS-I
, vol.55
, Issue.6
, pp. 1485-1494
-
-
Baeg, S.1
-
4
-
-
33144454816
-
Investigation of multi-bit upsets in a 150 nm technology SRAM device
-
DOI 10.1109/TNS.2005.860675
-
D. Radaelli, H. Puchner, S. Wong, and S. Daniel, "Investigation of multi-bit upsets in a 150 nm technology SRAM device," IEEE Trans. Nucl. Sci., vol.52, no.6, pp. 2433-2437, Dec. 2005. (Pubitemid 43269622)
-
(2005)
IEEE Transactions on Nuclear Science
, vol.52
, Issue.6
, pp. 2433-2437
-
-
Radaelli, D.1
Puchner, H.2
Wong, S.3
Daniel, S.4
-
5
-
-
0026896308
-
Compound-Poisson software reliability model
-
Jul.
-
M. Sahinoglu, "Compound-Poisson software reliability model," IEEE Trans. Softw. Eng., vol.18, no.7, pp. 624-630, Jul. 1992.
-
(1992)
IEEE Trans. Softw. Eng.
, vol.18
, Issue.7
, pp. 624-630
-
-
Sahinoglu, M.1
-
6
-
-
0033737766
-
Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's
-
Jun.
-
S. Satoh, Y. Tosaka, and A. Wender, "Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's," IEEE Electron Device Lett., vol.21, pp. 310-312, Jun. 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, pp. 310-312
-
-
Satoh, S.1
Tosaka, Y.2
Wender, A.3
-
7
-
-
77951024147
-
SRAM interleaving distance selection with a soft error failure model
-
Jyvaskyla, Finland, Sep.
-
S. Baeg, S. Wen, and R. Wong, "SRAM interleaving distance selection with a soft error failure model," in Proc. Eur. Workshop Radiation Effects Comp. Syst. (RADECS), Jyvaskyla, Finland, Sep. 2008, pp. 306-310.
-
(2008)
Proc. Eur. Workshop Radiation Effects Comp. Syst. (RADECS)
, pp. 306-310
-
-
Baeg, S.1
Wen, S.2
Wong, R.3
-
9
-
-
39049112433
-
Spreading diversity in multi-cell neutron-induced upsets with device scaling
-
DOI 10.1109/CICC.2006.321010, 4114997, Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
-
E. Ibe, S. Chung, S.Wen, H. Yamaguchi, Y. Yahagi, H. Kameyama, S. Yamamoto, and T. Akioka, "Spreading diversity in multi-cell neutroninduced upsets with device scaling," in Proc. IEEE Custom Integrated Circuit Conf., 2006, pp. 437-444. (Pubitemid 351246408)
-
(2006)
Proceedings of the Custom Integrated Circuits Conference
, pp. 437-444
-
-
Ibe, E.1
Chung, S.S.2
Wen, S.3
Yamaguchi, H.4
Yahagi, Y.5
Kameyama, H.6
Yamamoto, S.7
Akioka, T.8
-
10
-
-
33845565333
-
A reliability-enhanced TCAM architecture with associated embedded DRAM and ECC
-
DOI 10.1093/ietele/e89-c.11.1612
-
H. Noda, K. Dosaka, H. J. Mattausch, T. Koide, F. Morishita, and K. Arimoto, "A reliability-enhanced TCAM architecture with associated embedded DRAM and ECC," IEICE Trans. Electron., vol.E89-C, no.11, Nov. 2006. (Pubitemid 44934377)
-
(2006)
IEICE Transactions on Electronics
, vol.E89-C
, Issue.11
, pp. 1612-1619
-
-
Noda, H.1
Dosaka, K.2
Mattausch, H.J.3
Koide, T.4
Morishita, F.5
Arimoto, K.6
-
11
-
-
0037245512
-
A ternary contentaddressable memory(TCAM) based on 4T static storage and including a current-race sensing scheme
-
Jan.
-
I. Arsovski, T. Chandler, and A. Sheikholeslami, "A ternary contentaddressable memory(TCAM) based on 4T static storage and including a current-race sensing scheme," IEEE J. Solid-State Circuits, vol.38, no.1, pp. 155-158, Jan. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.1
, pp. 155-158
-
-
Arsovski, I.1
Chandler, T.2
Sheikholeslami, A.3
-
13
-
-
63449121595
-
A low-power ternary CAM with positive-feedback match-line sense amplifiers
-
Mar.
-
N. Mohan, W. Fung, D. Wright, and M. Sachdev, "A low-power ternary CAM with positive-feedback match-line sense amplifiers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.56, no.3, pp. 566-573, Mar. 2009.
-
(2009)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.56
, Issue.3
, pp. 566-573
-
-
Mohan, N.1
Fung, W.2
Wright, D.3
Sachdev, M.4
-
14
-
-
51649101771
-
Design techniques for mitigatiion of soft errors in differential switched-capacitor circuits
-
Sep.
-
P. Fleming, B. Olson, W. Holman, B. Bhuva, and L. Massengill, "Design techniques for mitigatiion of soft errors in differential switched-capacitor circuits," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.55, no.9, pp. 838-842, Sep. 2008.
-
(2008)
IEEE Trans. Circuits Syst. II, Exp. Briefs
, vol.55
, Issue.9
, pp. 838-842
-
-
Fleming, P.1
Olson, B.2
Holman, W.3
Bhuva, B.4
Massengill, L.5
-
15
-
-
26844493717
-
On reducing peak current and power during test
-
Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
-
W. Li, S. Reddy, and I. Pomeranz, "On reducing peak current and power during test," in Proc. IEEE Comp. Soc. Ann. Symp. VLSI, May 2005, pp. 156-161. (Pubitemid 41462620)
-
(2005)
Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI
, pp. 156-161
-
-
Li, W.1
Reddy, S.M.2
Pomeranz, I.3
-
16
-
-
0142246860
-
A case study of IR-drop in structured at-speed testing
-
Sep.
-
J. Saxena, K. Butler, V. Jayaram, and S. Kundu, "A case study of IR-drop in structured at-speed testing," in Proc. Int. Test Conf., Sep. 2003, pp. 1098-1104.
-
(2003)
Proc. Int. Test Conf.
, pp. 1098-1104
-
-
Saxena, J.1
Butler, K.2
Jayaram, V.3
Kundu, S.4
|