Defect tolerance based on coding and series replication in transistor-logic demultiplexer circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 11 SPEC. ISS., 2007, Pages 2410-2421

  Robinett, Warren ^a   Kuekes, Philip J ^a   Williams, R Stanley ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Error correction codes; Fault tolerance; Reliability; Transistor circuits

Indexed keywords

COMPUTER PROGRAMMING; DEFECTS; DEMULTIPLEXING; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; FAULT TOLERANCE; NANOELECTRONICS; RELIABILITY; TIMING CIRCUITS; TRANSISTORS;

DEFECT PROBABILITY; DEMULTIPLEXER CIRCUITS; ERROR CORRECTION CODES; FAILURE PROBABILITY; PERFORMANCE ANALYSIS; REDUNDANCY FACTORS; REPLICATION METHOD; TRANSISTOR CIRCUIT;

COMPUTER CIRCUITS;

EID: 64949104463     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.907865     Document Type: Article

References (22)

1. International Technology Roadmap for Semiconductors 2005 [Online]. Available: http://www.itrs.net/reports.html
2. A. DeHon, "Array-based architecture for fet-based, nanoscale electronics," IEEE Trans. Nanotechnol., vol. 2, no. 1, pp. 23-32, Mar. 2003.
3. K. Nikolic, A. Sadek, and M. Forshaw, "Architectures for reliable computing with unreliable nanodevices," in Proc. IEEE-NANO'01., 2001, pp. 254-259.
4. J. R. Heath, P. J. Kuekes, G. Snider, and R. S. Williams, "A defect tolerant computer architecture: Opportunities for nanotechnology," Sci, vol. 280, pp. 1717-1721, 1998.
5. G. Snider, P. Kuekes, T. Hogg, and R. Stanley Williams, "Nanoelectronic architectures," Appl. Phys. A, vol. 80, no. 6, pp. 1183-1195, Mar. 2005.
6. K. Chakraborty and P. Mazumder, Fault Tolerance and Reliability Techniques For High-Density Random-Access Memories. Upper Saddle River, NJ: Prentice-Hall, 2002.
7. D. P. Siewiorek and R. S. Swarz, Reliable Computer Systems: Design and Evaluation. Natick, MA: A. K. Peters, 1998, p. 165.
8. F. J. MacWilliams and N. J. A. Sloane, The Theory of Error-Correcting Codes. New York: North-Holland, 1990.
9. P. J. Kuekes, W. Robinett, G. Seroussi, and R. S. Williams, "Defecttolerant interconnect to nanoelectronic circuits: Internally redundant demultiplexers based on error-correcting codes," Nanotechnology, vol. 16, pp. 869-882, 2005.
10. M. Blaum and H. Van Tilborg, "On t-error correcting/all unidirectional error detecting codes," IEEE Trans. Comput., vol. 38, no. 11, pp. 1493-1501, Nov. 1989.
11. J. N. Hogan and R. M. Roth, "Fault-Tolerant address logic for solid state memory" US Patent # 6459648, 2002.
12. J. von Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," in Automata Studies, C. E. Shannon and J. McCarthy, Eds. :, 1955, pp. 43-98.
13. E. F. Moore and C. E. Shannon, "Reliable circuits using less reliable relays," J. Franklin Inst., pp. 191-208, 1956, and 281-297.
14. K. Nikolic, A. Sadek, and M. Forshaw, "Fault-tolerant techniques for nanonanocomputers," Nanotechnology, vol. 13, pp. 357-362, 2002.
15. J. Han and P. Jonker, "A defect- and fault-tolerant architecture for nanocomputers," Nanotechnology, vol. 14, no. 2, pp. 224-230, Feb. 1, 2003.
16. A. DeHon and H. Naeimi, "Seven strategies for tolerating highly defective fabrication," IEEE Des. Test Comput, vol. 22, no. 4, pp. 306-315, Apr. 2005.
17. Z. Zhong, D. Wang, Y. Cui, M. W. Bockrath, and C. M. Lieber, "Nanowire crossbar arrays as address decoders for integrated nanosystems," Sci vol. 302, pp. 13771379, 2003.
18. P. J. Kuekes, W. Robinett, and R. S. Williams, "Improved voltage margins using linear error-correcting codes in resistor-logic demultiplexers for nanoelectronics," Nanotechnology, vol. 16, pp. 1419-1432, 2005.
19. P. J. Kuekes, W. Robinett, G. Seroussi, and R. S.Williams, "Defect tolerance in resistor-logic demultiplexers for nanoelectronics," Nanotechnology, vol. 17, pp. 2466-2474, 2006.
20. P. J. Kuekes, W. Robinett, R. M. Roth, G. Seroussi, G. S. Snider, and R. S. Williams, "Resistor-logic demultiplexers for nanoelectronics based on constant-weight codes," Nanotechnology, vol. 17, pp. 1052-1061, 2006.
21. K. J. Sullivan, J. B. Dugan, and D. Coppit, "The galileo fault tree analysis tool," in Proc. 29th Annu. Int. Symp. Fault-Tolerant Comput., Madison, WI, 1999, pp. 232-235.
22. D. Jaffe, Information About Binary Linear Codes 2006 [Online]. Available: http://www.math.unl.edu/~djaffe/codes/webcodes/codeform.html