Task scheduling model and algorithm based on dual-Vdd dynamic reconfigurable FPGA

Zhejiang Daxue Xuebao(Gongxue Ban)/Journal of Zhejiang University (Engineering Science)

Volumn 44, Issue 2, 2010, Pages 300-304

  Xu, Ke Jun ^a   Xu, Wen Yao ^a   Shen, Ji Zhong ^a   Xu, Xin Min ^a  

^a ZHEJIANG UNIVERSITY   (China)

Author keywords

Dual supply voltage field programmable gate array (FPGA); First fit decreasing algorithm; Hardware task scheduling; Partially dynamic reconfiguration

Indexed keywords

DUAL-SUPPLY VOLTAGE FIELD PROGRAMMABLE GATE ARRAY (FPGA); DYNAMIC RE-CONFIGURATION; FIRST-FIT-DECREASING ALGORITHM; SUPPLY VOLTAGES; TASK-SCHEDULING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; MULTITASKING; OPTICAL SENSORS; SCHEDULING ALGORITHMS;

DYNAMIC MODELS;

EID: 77950562428     PISSN: 1008973X     EISSN: None     Source Type: Journal    
DOI: 10.3785/j.issn.1008-973X.2010.02.016     Document Type: Article

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