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Volumn 2006, Issue , 2006, Pages 618-623

DraXRouter: Global routing in X-architecture with dynamic resource assignment

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; INTEGRATED CIRCUITS; MATHEMATICAL INSTRUMENTS; OPTIMIZATION; PROBLEM SOLVING; ROUTERS;

EID: 33748627691     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (13)

References (20)
  • 2
    • 2942665618 scopus 로고    scopus 로고
    • A new paradigm for general architecture routing
    • April 26-28, Boston, Massachusetts, USA
    • Martin Paluszewski, Pawel Winter, Martin Zachariasen. A New Paradigm for General Architecture Routing. GLSVLSI '04, April 26-28, 2004, Boston, Massachusetts, USA.
    • (2004) GLSVLSI '04
    • Paluszewski, M.1    Winter, P.2    Zachariasen, M.3
  • 3
    • 33748592176 scopus 로고    scopus 로고
    • Labyrinth, http://www.ece.ucsb.edu/~kastner/labyrinth/
  • 4
    • 0033703013 scopus 로고    scopus 로고
    • Manhattan or non-Manhattan? A study of alternative VLSI routing architectures
    • Chicago, IL, USA
    • Cheng-Kok Koh and P. H. Madden. Manhattan or non-Manhattan? a study of alternative VLSI routing architectures. In Proceedings of the 10th ACM GLSVLSI, pages 47-52, Chicago, IL, USA, 2000.
    • (2000) Proceedings of the 10th ACM GLSVLSI , pp. 47-52
    • Koh, C.-K.1    Madden, P.H.2
  • 5
    • 22544443621 scopus 로고    scopus 로고
    • Spanning graph based non-rectilinear steiner tree algorithms
    • Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang. Spanning Graph Based Non-Rectilinear Steiner Tree Algorithms. IEEE Trans. on CAD. 2005, 24(7).
    • (2005) IEEE Trans. on CAD. , vol.24 , Issue.7
    • Zhu, Q.1    Zhou, H.2    Jing, T.3    Hong, X.4    Yang, Y.5
  • 6
    • 0026927206 scopus 로고
    • Hierarchical steiner tree construction in uniform orientations
    • Majid Sarrafzadeh, C. K. Wong, Hierarchical Steiner Tree Construction in Uniform Orientations. IEEE Trans. on CAD, 11(9): pp.1095-1103, 1992.
    • (1992) IEEE Trans. on CAD , vol.11 , Issue.9 , pp. 1095-1103
    • Sarrafzadeh, M.1    Wong, C.K.2
  • 7
    • 84954448351 scopus 로고    scopus 로고
    • The Y-architecture: Yet another on-chip interconnect solution
    • Kitakyushu, Japan
    • H. Chen, F Zhou and C. K. Cheng. The Y-architecture: yet another on-chip interconnect solution. In Proceedings of the ASP-DAC, pages 840-846, Kitakyushu, Japan, 2003.
    • (2003) Proceedings of the ASP-DAC , pp. 840-846
    • Chen, H.1    Zhou, F.2    Cheng, C.K.3
  • 8
    • 11244299747 scopus 로고    scopus 로고
    • An efficient rectilinear steiner minimum tree algorithm based on ant colony optimization
    • Chengdu, China
    • Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan. An Efficient Rectilinear Steiner Minimum Tree Algorithm Based on Ant Colony Optimization. In: Proceedings of IEEE ICCCAS, 2004, Chengdu, China, 1276-1280.
    • (2004) Proceedings of IEEE ICCCAS , pp. 1276-1280
    • Hu, Y.1    Jing, T.2    Hong, X.3    Feng, Z.4    Hu, X.5    Yan, G.6
  • 9
    • 26444490792 scopus 로고    scopus 로고
    • Performance-oriented layout design, pervasive use of diagonal interconnects reduces wire-length
    • T. Mitsuhashi, K. Someha: Performance-oriented layout design, pervasive use of diagonal interconnects reduces wire-length. Design Wave Magazine (2001) 59-64
    • (2001) Design Wave Magazine , pp. 59-64
    • Mitsuhashi, T.1    Someha, K.2
  • 10
    • 33748613659 scopus 로고    scopus 로고
    • A routing paradigm with novel resources estimation and routability models for X-architecture based physical design
    • Samos, Greece
    • Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, and Guiying Yan. A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS V, Samos, Greece, 2005.
    • (2005) SAMOS V
    • Hu, Y.1    Jing, T.2    Hong, X.3    Hu, X.4    Yan, G.5
  • 14
    • 33748614204 scopus 로고    scopus 로고
    • The x initiative, http://www.xinitiative.org.
  • 15
    • 26444458046 scopus 로고    scopus 로고
    • Congestion reduction in traditional and new routing architectures
    • Washington, DC, USA
    • A. R. Agnihotri and P. H. Madden. Congestion reduction in traditional and new routing architectures. In Proceedings of the 13th ACM GLSVLSI, pages 28-29, Washington, DC, USA, 2003.
    • (2003) Proceedings of the 13th ACM GLSVLSI , pp. 28-29
    • Agnihotri, A.R.1    Madden, P.H.2
  • 18
    • 26444490792 scopus 로고    scopus 로고
    • Performance- Oriented layout design, pervasive use of diagonal interconnects reduces wire- length
    • September
    • Takashi Mitsuhashi and Kenji Someha. Performance- Oriented Layout Design, Pervasive Use of Diagonal Interconnects Reduces Wire- Length, Design Wave Magazine, pages 59-64, September, 2001.
    • (2001) Design Wave Magazine , pp. 59-64
    • Mitsuhashi, T.1    Someha, K.2
  • 20
    • 27944488299 scopus 로고    scopus 로고
    • Multilevel full-chip routing for the X-based architecture
    • June 13-17, Anaheim, CA, USA
    • Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang and Sao-Jie Chen. Multilevel Full-Chip Routing for the X-Based Architecture. DAC 2005, pages597-602, June 13-17, 2005, Anaheim, CA, USA.
    • (2005) DAC 2005 , pp. 597-602
    • Ho, T.-Y.1    Chang, C.-F.2    Chang, Y.-W.3    Chen, S.-J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.