SEU-induced persistent error propagation in FPGAs

IEEE Transactions on Nuclear Science

Volumn 52, Issue 6, 2005, Pages 2438-2445

  Morgan, Keith ^a,b   Caffrey, Michael ^a   Graham, Paul ^a   Johnson, Eric ^a,b   Pratt, Brian ^a,b   Wirthlin, Michael ^c  

^a LOS ALAMOS NATIONAL LABORATORY   (United States)

^b BRIGHAM YOUNG UNIVERSITY   (United States)

^c Department of Electrical and Computer Engineering   (United States)

Author keywords

Dynamic testing; Error propagation; FPGA; Persistence; Proton accelerator; Radiation; Simulator; Single event upset (SEU)

Indexed keywords

PARTICLE ACCELERATORS; PROTONS; RELIABILITY; SIMULATORS;

DYNAMIC TESTING; ERROR PROPAGATION; PERSISTENCE; SINGLE-EVENT UPSET (SEU);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33144470738     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.860674     Document Type: Conference Paper

References (16)

1. N. Rollins, M. Wirthlin, M. Caffrey, and P. Graham, "Evaluating TMR techniques in the presence of single event upsets," in Proc. 6th Annu. Int. Conf Military and Aerospace Programmable Logic Devices (MAPLD), NASA Office of Logic Design, AIAA, Washington, D.C., Sep. 2003, p. P63.
2. C. Carmichael, "Triple module redundancy design techniques for Virtex FPGAs," Xilinx Corp., Tech. Rep. xAPP197 (vl.O), Nov. 1, 2001.
3. P. K. Samudrala, J. Ramos, and S. Katkoori, "Selective triple modular redundancy for SEU mitigation in FPGAs," in Proc. 6th Annu. Int. Conf. Military and Aerospace Programmable Logic Devices (MAPLD), NASA Office of Logic Design, AIAA, Washington, D.C., 2003, p. C1.
4. "Qpro Virtex 2.5v radiation hardened FPGAs," Xilinx Corp., Tech. Rep., dS028 (vl.2), Nov. 5, 2001.
5. E. Johnson, M. Caffrey, P. Graham, N. Rollins, and M. Wirthlin, "Accelerator validation of an FPGA SEU simulator," IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp. 2147-2157, Dec. 2003.
6. M. Wirthlin, E. Johnson, N. Rollins, M. Caffrey, and P. Graham, "The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets," in IEEE Symp. Field-Programmable Custom Computing Machines, K. Pocek and J. Arnold, Eds. Napa, CA, Apr. 2003, pp. 133-142.
7. E. Johnson, K. Morgan, N. Rollins, M. Wirthlin, M. Caffrey, and P. Graham, "Detection of configuration memory upsets causing persistent errors in SRAM-based FPGAs," in Proc. MAPLD Conf., Sep. 2004. Paper P135.
8. A. Holmes-Siedle and L. Adams, Handbook of Radiation Effects, 2nd ed. Oxford, U.K.: Oxford Univ. Press, 2002.
9. E. Johnson, M. J. Wirthlin, and M. Caffrey, "Single-event upset simulation on an FPGA," in Proc. Int. Conf. Engineering of Reconfigurable Systems and Algorithms (ERSA), T. P. Plaks and P. M. Athanas, Eds, Jun. 2002, pp. 68-73.
10. T. L. Turflinger and M. V Davey, "Understanding single event phenomena in complex analog and digital integrated circuits," IEEE Trans. Nucl Sci., vol. 37, no. 6, pp. 1832-1838, Dec. 1990.
11. C. Carmichael, M. Caffrey, and A. Salazar, "Correcting single-event upsets through Virtex partial configuration," Xilinx Corp., Tech. Rep. XAPP216 (vl.O), Jun. 1, 2000.
12. R. Baumann, "Single-event effects in advanced cmos technology, " presented at the IEEE NSREC Short Course, Seattle, WA, Jul. 2005.
13. Correlation of fault-injection to proton accelerator persistent cross section measurements. (2005, Jul.). [Online], Available: http://dspace.byu.edu
14. Predicting on-orbit SEU rates. (2005, Jul.). [Online]. Available:http://dspace.byu.edu
15. E. Fuller, M. Caffrey, A. Salazar, C. Carmichael, and J. Fabula, "Radiation testing update, SEU mitigation, and availability analysis of the Virtex FPGA for space reconfigurable computing," in Proc. 3rd Annu. Conf. Military and Aerospace Programmable Logic Devices (MAPLD), 2000, p. P30.
16. N. Rollins, M. Wirthlin, and P. Graham, "Evaluation of power costs in triplicated FPGA designs," in Proc. MAPLD Conf., Sep. 2004. Paper P136.