Routability checking for three-dimensional architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 12, 2004, Pages 1371-1374

  Hung, William N N ^a   Song, Xiaoyu ^b   Kam, Timothy ^c   Cheng, Lerong ^b   Yang, Guowu ^b  

^a Synplicity Inc   (United States)

^b PORTLAND STATE UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Computer aided design (CAD); Layout; Routability; Satisfiability

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; FIELD PROGRAMMABLE GATE ARRAYS; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MULTICHIP MODULES; PRINTED CIRCUIT BOARDS; THEOREM PROVING; VECTORS;

BOOLEAN FORMULATIONS; GRID LINES; ROUTABILITY; STATISFIABILITY;

VLSI CIRCUITS;

EID: 12344263897     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.837999     Document Type: Article

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