Reliability analysis of large circuits using scalable techniques and tools

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 11 SPEC. ISS., 2007, Pages 2447-2460

  Bhaduri, Debayan ^a   Shukla, Sandeep K ^a   Graham, Paul S ^b   Gokhale, Maya B ^b,c  

^a State University   (United States)

^b LOS ALAMOS NATIONAL LABORATORY   (United States)

^c LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

Author keywords

Circuit; CMOS; Computer aided design (CAD); Defects; Methodologies; Nanoscale; Nanotechnology; Probabilistic model checking (PMC); Probability; Reliability; Scalability; Scalable, Extensible Tool for Reliability Analysis (SETRA); Techniques; Tool

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED ANALYSIS; COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; DEFECTS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; MODEL CHECKING; NANOELECTRONICS; NANOTECHNOLOGY; NETWORKS (CIRCUITS); PROBABILITY; RELIABILITY; SCALABILITY; TIMING CIRCUITS; TOOLS; TRANSFER MATRIX METHOD;

METHODOLOGIES; NANO SCALE; PROBABILISTIC MODEL CHECKING; SCALABLE, EXTENSIBLE TOOL FOR RELIABILITY ANALYSIS (SETRA); TECHNIQUES;

RELIABILITY ANALYSIS;

EID: 44949151062     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.907863     Document Type: Article

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