Device and architecture concurrent optimization for FPGA transient soft error rate

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 194-198

  Lin, Yan ^a   He, Lei ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-LEVEL; CIRCUIT ELEMENTS; CMOS SCALING; COMPUTER-AIDED DESIGN; CONFIGURATION MEMORY; DEVICE RELIABILITY; FPGA ARCHITECTURES; INTERNATIONAL CONFERENCES; SER EVALUATION; SOFT ERROR RATES; SOFT ERRORS;

DESIGN; ERROR ANALYSIS; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LEARNING SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION;

ARCHITECTURE;

EID: 50249151499     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397265     Document Type: Conference Paper

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