Design dependent process monitoring for back-end manufacturing cost reduction

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2010, Pages 116-122

  Chan, Tuck Boon ^a   Pant, Aashish ^a   Cheng, Lerong ^b   Gupta, Puneet ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SanDisk Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; PROCESS CONTROL; PROCESS MONITORING;

DEPENDENT PROCESS; DESIGN PERFORMANCE; MANUFACTURING COST; MONITORING STRATEGY; MONITORING STRUCTURES; PREDICTION SCHEMES; PROCESS DEVIATIONS; WAFER FABRICATIONS;

COST REDUCTION;

EID: 78650874312     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2010.5654280     Document Type: Conference Paper

References (22)

1. M. Bhushan, A. Gattiker, M. B. Ketchen and K.K. Das, "Ring Oscillators for CMOS Process Tuning and Variability Control," in IEEE Trans. on Semiconductor Manufacturing, vol. 1, no. 1, pp. 10-19, Feb. 2006.
2. M.B. Ketchen, M. Bhushan and D. Pearson, "High Speed Test Structures for In-Line Process Monitoring and Model Calibration,. in Intl. Conf. on Microelectronic Test Structures, pp.33-38, Apr. 2005.
3. R. Lefferts and C. Jakubiec, "An Integrated Test Chip for the Complete Characterization and Monitoring of a 0.25um CMOS Technology that fits into five scribe line structures 150um by 5000 um," in ICMTS,Mar. 2003.
4. A.J. Drake, R.M. Senger, H. Singh, G.D. Carpenter and N.K. James, "Dynamic Measurement of Critical-Path Timing,. in IEEE ICICDT, pp. 249-252,June 2008.
5. C. Visweswariah, K. Ravindran, K. Kalafala, S.G. Walker, S. Narayan, D.K. Beece et. al., "First-order Incremental Block-Based Statistical Timing Analysis,. in IEEE trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, issue 10, pp. 2170-2180, Oct. 2006.
6. S. Mitra, E. Volkerink, E.J. McCluskey and S. Eichenberger, "Delay Defect Screening using Process Monitoring Structures," in Proc. of VLSI Test Synposium, pp. 43-48, Apr. 2004.
7. Q. Liu, S.S. Sapatnekar, "Synthesizing a Representative Critical Path for Post-Silicon Delay Prediction," in IEEE/ACM ISPED, Mar. 2009.
8. F. Rigaud, J.M. Portal, H. Aziza, et. al., "Test Structure for Process and Product Evaluation," IEEE Intl. Conf. on Microelectronic Test Structures, Mar., 2007.
9. C.Y. Cho, D.D. Kim, J.H. Kim D.Y. Lim and S.Y. Cho,"Early Prediction of Product Performance and Yield Via Technology Benchmark," in IEEE Custom Intergrated Circutis Conference, pp. 205-208, Sept., 2008.
10. K.K. Das, S.G. Walker and M. Bhushan, "An Integrated CAD methodology for Evaluating Mosfet and Parasitic Extraction Models and Variabilitiy,. in Proc. of IEEE, vol. 95, issue 3, pp.670-687, Mar., 2007.
11. M.H. Na, E.J. Nowak, W. Haensch and J. Cai, "The Effective Drive Current in Cmos Inverters,. in IEEE IEDM, pp. 121-124, 2002.
12. K. v. Arnim, C. Pacha, K. Hofmann, T. Schulz, K. Schrfer and J. Berthold, "An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits,. in IEDM,Dec 2007.
13. +) and Capacitance Methodology for Cmos Circuit Performance Prediction and Model-to-Hardware Correlation," in IEEE IEDM, pp. 1-4, Dec., 2008.
14. S. Reda, S. R. Nassif, "Analyzing the Impact of Process Variations on Parametric Measurements: Novel Models and Applications,. in IEEE DATE, 2009.
15. X. Li, R. Rurenbar and S. Blanton, "Virtual Probe: A Statistically Optimal Framework for Minimum-Cost Silicon Characterization of Nanoscale Integrated Circuits,. in IEEE ICCAD, Nov. 2009.
16. L. Cheng, P. Gupta, C. Spanos, K. Qian and L. He, "Physically Justifiable Die-Level modeling of Spatial Variation in View of Systematic AcrossWafer Variability," IEEE Design Automation Conference, pp. 104-108, July, 2009.
17. Y. Cao, P. Gupta et. al. ,"Design Sensitivities to variability: Extrapolation and assessments in nanometer VLSI," IEEE ASIC/SoC Conference, Sept., 2002.
18. W. Zhao, Y. Chao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif and K. Nowka, "Rigorous extraction of process variations for 65nm CMOS design," in European Solid State Device Research Conf.,Sept., 2007.
19. M. Ketchen, M. Bhushan and D. Pearson, "High Speed Test Structures for In-Line Process Monitoring and Model Calibration," in ICMTS, April 2005
20. T.B. Chan, R.S. Ghaida and P. Gupta, "Electrical Modeling of Lithographic Imperfections," in Proc IEEE/ACM VLSI Design Conference,pp. 423-428, Jan. 2010
21. Nangate Open Cell Library,https://www.nangate.com/.
22. R. Rao, A. Devgan, D. Blaauw and D. Sylvester, "Parametric Yield Estimation Considering Leakage Variability", Design Automation Conference, June 2004.