-
1
-
-
0015622088
-
How big should a printed circuit board be?
-
Sutherland, N. and Oesticher, N. (1973) How big should a printed circuit board be? IEEE Trans. Comput., C-22, 537-741.
-
(1973)
IEEE Trans. Comput.
, vol.C-22
, pp. 537-741
-
-
Sutherland, N.1
Oesticher, N.2
-
2
-
-
0019530332
-
Two-dimensional stochastic model for interconnections in master slice integrated circuits
-
Gamal, A. (1981) Two-dimensional stochastic model for interconnections in master slice integrated circuits. IEEE Trans. Circuits Syst., CAS I-28 (2), 127-138.
-
(1981)
IEEE Trans. Circuits Syst.
, vol.CASI-28
, Issue.2
, pp. 127-138
-
-
Gamal, A.1
-
3
-
-
0019610041
-
A stochastic model for interconnections in custom integrated circuits
-
Gamal, A. and Syed, Z. (1981) A stochastic model for interconnections in custom integrated circuits. IEEE Trans. Circuits Syst., CAS I-28, 888-894.
-
(1981)
IEEE Trans. Circuits Syst.
, vol.CAS I-28
, pp. 888-894
-
-
Gamal, A.1
Syed, Z.2
-
4
-
-
0024479018
-
Techniques for area estimation of VLSI layouts
-
Kurdahi, F. and Parker, A. (1986) Techniques for area estimation of VLSI layouts. IEEE Trans. Comput. Aid. D., 8(1), 81.
-
(1986)
IEEE Trans. Comput. Aid. D.
, vol.8
, Issue.1
, pp. 81
-
-
Kurdahi, F.1
Parker, A.2
-
5
-
-
0017972983
-
Prediction of wiring space requirements of LSI
-
Heller, W., Mikhail, W. and Donath, W. (1980) Prediction of wiring space requirements of LSI. J. Des. Autom. Fault, 2 (2),117-144.
-
(1980)
J. Des. Autom. Fault
, vol.2
, Issue.2
, pp. 117-144
-
-
Heller, W.1
Mikhail, W.2
Donath, W.3
-
6
-
-
0033691573
-
Wire space estimation and routability analysis
-
Song, X., Tang, Q., Zhou, D. and Wang, Y. (2000) Wire space estimation and routability analysis. IEEE Trans. Comput. Aid. D., 19(5), 624-628.
-
(2000)
IEEE Trans. Comput. Aid. D.
, vol.19
, Issue.5
, pp. 624-628
-
-
Song, X.1
Tang, Q.2
Zhou, D.3
Wang, Y.4
-
7
-
-
0033703894
-
Wiring space and length estimation in two-dimensional arrays
-
Cho, J. (2000) Wiring space and length estimation in two-dimensional arrays. IEEE Trans. Comput. Aid. D., 19(5), 612-615.
-
(2000)
IEEE Trans. Comput. Aid. D.
, vol.19
, Issue.5
, pp. 612-615
-
-
Cho, J.1
-
8
-
-
0036179948
-
Estimating routing congestion using probabilistic analysis
-
Lou, J., Thakur, S., Krishnamoorthy, S. and Sheng, H. (2002) Estimating routing congestion using probabilistic analysis. IEEE Trans. Comput. Aid. D., 21(1), 32-41.
-
(2002)
IEEE Trans. Comput. Aid. D.
, vol.21
, Issue.1
, pp. 32-41
-
-
Lou, J.1
Thakur, S.2
Krishnamoorthy, S.3
Sheng, H.4
-
9
-
-
2442485708
-
A fast congestion estimator for routing with bounded detours
-
Yokohama, Japan, January 27-30, IEEE, USA
-
Cheng, L., Song, X., Yang, G. and Tang, Z. (2004) A fast congestion estimator for routing with bounded detours. In Proc. ASP-DAC 2004, Yokohama, Japan, January 27-30, pp. 666-670. IEEE, USA.
-
(2004)
Proc. ASP-DAC 2004
, pp. 666-670
-
-
Cheng, L.1
Song, X.2
Yang, G.3
Tang, Z.4
-
10
-
-
4544322256
-
Congestion Estimation for 3D Routing
-
Lafayette, LA, February 19-20, IEEE Computer Society, USA
-
Cheng, L., Hung, W., Yang, G. and Song, X. (2004) Congestion Estimation for 3D Routing. In Proc. ISVLSI 2004, Lafayette, LA, February 19-20, pp. 239-240. IEEE Computer Society, USA.
-
(2004)
Proc. ISVLSI 2004
, pp. 239-240
-
-
Cheng, L.1
Hung, W.2
Yang, G.3
Song, X.4
-
12
-
-
27844553497
-
-
UCLA
-
UCLA, http://www.ece.ucsb.edu/~kastner/labyrinth/.
-
-
-
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