Low-energy GALS NoC with FIFO - Monitoring dynamic voltage scaling

Microelectronics Journal

Volumn 42, Issue 6, 2011, Pages 889-896

  Rahimi, Abbas ^a   Salehi, Mostafa E ^b   Mohammadi, Siamak ^c   Fakhraie, Sied Mehdi ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b ISLAMIC AZAD UNIVERSITY   (Iran)

^c UNIVERSITY OF TEHRAN   (Iran)

Author keywords

Dynamic voltage scaling; GALS NoC; Low energy

Indexed keywords

CMOS TECHNOLOGY; DYNAMIC VOLTAGE SCALING; DYNAMIC VOLTAGE SCALING POLICIES; ENERGY DELAY PRODUCT; GALS NOC; IMPLEMENTATION COST; LINK UTILIZATION; LOW ENERGIES; LOW ENERGY; SATURATED NETWORK; SPICE SIMULATIONS; SUPPLY VOLTAGES; SWITCH ARCHITECTURES; THRESHOLD LEVELS; VOLTAGE LEVELS;

CMOS INTEGRATED CIRCUITS; DECISION MAKING; NETWORK ARCHITECTURE; ROUTERS; SPICE;

VOLTAGE STABILIZING CIRCUITS;

EID: 79956372269     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2011.03.016     Document Type: Article

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