A low cost network-on-chip with guaranteed service well suited to the GALS approach

2006 1st International Conference on Nano-Networks and Workshops, Nano-Net

Volumn , Issue , 2006, Pages

  Miro Panades, Ivan ^a   Greiner, Alain ^b   Sheibanyrad, Abbas ^b  

^a STMICROELECTRONICS   (France)

^b SORBONNE UNIVERSITÉ   (France)

Author keywords

Bi synchronous FIFO; DSPIN; GALS; Globally asynchronous locally synchronous; Mesochronous; Network on chip; NoC; SoC; SPIN; System on chip

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; PACKET SWITCHING;

BI-SYNCHRONOUS FIFO; DSPIN; GALS; GALS APPROACH; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; GUARANTEED SERVICES; GUARANTEED THROUGHPUT; INTERNATIONAL CONFERENCES; LOW COSTS; MESOCHRONOUS; MULTI-PROCESSORS; NANO-NET; NANO-NETWORKS; NETWORK ON CHIP; NETWORK ON CHIPS; NOC; REAL-TIME APPLICATIONS; SOC; SPIN; SYSTEM DESIGNERS; SYSTEM ON CHIP; SYSTEMS ON CHIPS;

REAL TIME SYSTEMS;

EID: 50149096693     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANONET.2006.346219     Document Type: Conference Paper

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