Two efficient synchronous ⇔ asynchronous converters well-suited for network on chip in GALS architectures

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4148 LNCS, Issue , 2006, Pages 191-202

  Sheibanyrad, A ^a   Greiner, A ^a  

^a SORBONNE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS MACHINERY; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; ROBUSTNESS (CONTROL SYSTEMS); THROUGHPUT;

GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS); LOW LATENCY CONVERTERS; MULTI PROCESSOR SYSTEM; SYNCHRONOUS COMMUNICATION PROTOCOL;

ANALOG TO DIGITAL CONVERSION;

EID: 33750087295     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11847083_19     Document Type: Conference Paper

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