Hiding synchronization delays in a GALS processor microarchitecture

Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 10, Issue , 2004, Pages 159-169

  Semeraro, Greg ^a   Albonesi, David H ^b   Magklis, Grigorios ^c   Scott, Michael L ^c   Dropsho, Steven G ^c   Dwarkadas, Sandhya ^c  

^a Kate Gleason College of Engineering   (United States)

^b Department of Electrical Engineering ^*

^c University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS); MULTIPLE CLOCK DOMAINS (MCD); PROCESSOR MICROARCHITECTURE;

COMPUTER ARCHITECTURE; DATA REDUCTION; INTERFACES (COMPUTER); PRODUCT DESIGN; SYNCHRONIZATION;

MICROPROCESSOR CHIPS;

EID: 2942635598     PISSN: 15228681     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

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