-
1
-
-
0034316092
-
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors
-
Nov./Dec
-
D. M. Brooks et al. Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro, 20(6), Nov./Dec. 2000.
-
(2000)
IEEE Micro
, vol.20
, Issue.6
-
-
Brooks, D.M.1
-
5
-
-
0034853842
-
Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols
-
June
-
T. Chelcea and S. M. Nowick. Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. In Design Automation Conference, June 2001.
-
(2001)
Design Automation Conference
-
-
Chelcea, T.1
Nowick, S.M.2
-
6
-
-
31344469393
-
A 90-nm Variable Frequency Clock System for a Power-Managed Itanium Architecture Processor
-
Jan
-
T. Fischer et al. A 90-nm Variable Frequency Clock System for a Power-Managed Itanium Architecture Processor. IEEE Journal of Solid State Circuits, 41(1), Jan. 2006.
-
(2006)
IEEE Journal of Solid State Circuits
, vol.41
, Issue.1
-
-
Fischer, T.1
-
9
-
-
18744371945
-
Area-Efficient Linear Regulator with Ultra-Fast Load Regulation
-
April
-
P. Hazucha et al Area-Efficient Linear Regulator with Ultra-Fast Load Regulation. IEEE Journal of Solid-State Circuits, 40(4), April 2005.
-
(2005)
IEEE Journal of Solid-State Circuits
, vol.40
, Issue.4
-
-
Hazucha, P.1
-
10
-
-
34247221770
-
Lowering Power Consumption in Clock by Using Globally Synchronous Locally Synchronous Design Style
-
June
-
A. Hemani et al. Lowering Power Consumption in Clock by Using Globally Synchronous Locally Synchronous Design Style. In Conference on Design Automation, June 1999.
-
(1999)
Conference on Design Automation
-
-
Hemani, A.1
-
11
-
-
0036294823
-
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
-
May
-
A. Iyer and D. Marculescu. Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors. In International Symposium on Computer Architecture, May 2002.
-
(2002)
International Symposium on Computer Architecture
-
-
Iyer, A.1
Marculescu, D.2
-
13
-
-
0033699240
-
A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
-
May
-
T. Olsson et al. A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs. In International Symposium on Circuits and Systems, May 2000.
-
(2000)
International Symposium on Circuits and Systems
-
-
Olsson, T.1
-
15
-
-
17644385095
-
Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture
-
Nov
-
G. Semeraro et al. Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture. In International Symposium on Microarchitecture, Nov. 2002.
-
(2002)
International Symposium on Microarchitecture
-
-
Semeraro, G.1
-
17
-
-
0345272496
-
Energy Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling
-
Feb
-
G. Semeraro et al. Energy Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. In International Symposium on High-Performance Computer Architecture, Feb. 2002,
-
(2002)
International Symposium on High-Performance Computer Architecture
-
-
Semeraro, G.1
-
18
-
-
0003450887
-
CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. WRL Research Report 2001/2
-
Aug
-
P. Shivakumar and N. P. Jouppi. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. WRL Research Report 2001/2, Aug. 2001.
-
(2001)
-
-
Shivakumar, P.1
Jouppi, N.P.2
-
21
-
-
34249306904
-
HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects
-
Technical Report CS-2003-05, Dept. of Computer Science, University of Virginia, Mar
-
Y. Zhang et al. HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Technical Report CS-2003-05, Dept. of Computer Science, University of Virginia, Mar. 2003.
-
(2003)
-
-
Zhang, Y.1
|