CHIPPER: A low-complexity bufferless deflection router

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2011, Pages 144-155

  Fallin, Chris ^a   Craik, Chris ^a   Mutlu, Onur ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AGE-BASED; AREA REDUCTION; BACK PRESSURES; CACHE MISS; CHIP MULTIPROCESSOR; CONTROL LOGIC; CRITICAL PATHS; DEFLECTION ROUTINGS; DESIGN TRADEOFF; DESKTOP APPLICATIONS; ENERGY CONSUMPTION; HARDWARE COST; HIGH COSTS; LARGE POWER; LIVELOCK FREEDOM; LOW-COMPLEXITY; MICRO ARCHITECTURES; MULTITHREADED; NETWORK LOAD; NETWORK POWER; NETWORKS ON CHIPS; PERFORMANCE DEGRADATION; PERMUTATION NETWORK; POWER REDUCTIONS; REASSEMBLY; ROUTER ARCHITECTURE; ROUTER BUFFER; THREE PROBLEMS; TOKEN-PASSING;

DEFLECTION (STRUCTURES); DEGRADATION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; MULTIPROGRAMMING; NETWORK ARCHITECTURE; NETWORK ROUTING;

COMPUTER ARCHITECTURE;

EID: 79955909866     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749724     Document Type: Conference Paper

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