Evaluating bufferless flow control for on-chip networks

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2010, Pages 9-16

  Michelogiannakis, George ^a   Sanchez, Daniel ^a   Dally, William J ^a   Kozyrakis, Christos ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENT; LIGHT LOADS; ON-CHIP NETWORKS; PACKET-SWITCHED; PER UNIT; POWER CONSUMED; PROCESS CONSTRAINTS; ROUTER BUFFER; ROUTING SCHEME;

ENERGY EFFICIENCY; MICROPROCESSOR CHIPS;

FLOW CONTROL;

EID: 77955102506     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2010.10     Document Type: Conference Paper

References (24)

1. J. Balfour and W. J. Dally, "Design tradeoffs for tiled CMP on-chip networks," in Proc. of the 20th annual Intl. Conf. on Supercomputing, 2006.
2. P. Baran, "On distributed communication networks," in IEEE Trans. on communication systems, 1964.
3. D. U. Becker and W. J. Dally, "Allocator implementations for network-on-chip routers," in Proc. of the Conf. on High Performance Computing Networking, Storage and Analysis, 2009.
4. C. Busch, M. Herlihy, and R. Wattenhofer, "Routing without flow control," in Proc. of the 13th annual ACM Symp. on Parallel Algorithms and Architectures, 2001.
5. W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, 2003.
6. W. J. Dally, "Virtual-channel flow control," IEEE Trans. on Parallel and Distributed Systems, vol. 3, no. 2, 1992.
7. W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. of the 38th annual Design Automation Conf., 2001.
8. C. Gomez, M. Gomez, P. Lopez, and J. Duato, "BPS: A bufferless switching technique for NoCs," in Workshop on Interconnection Network Architectures, 2008.
9. C. Gómez, M. E. Gómez, P. López, and J. Duato, "Reducing packet dropping in a bufferless NoC," in Proc. of the 14th intl. Euro-Par conf. on Parallel Processing, 2008.
10. A. Hansson, K. Goossens, and A. Rǎdulescu, "Avoiding message-dependent deadlock in network-based systems on chip," VLSI Design, 2007.
11. R. Ho, K. Mai, and M. Horowitz, "Efficient on-chip global interconnects," in Symp. on VLSI Circuits, 2003.
12. International Technology Roadmap for Semiconductors, 2007 Edition, www.itrs.net.
13. A. Kahng, B. Li, L.-S. Peh, and K. Samadi, "Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration," in Proc. of the conf. on Design, Automation and Test in Europe, 2009.
14. J. Kim, W. J. Dally, and D. Abts, "Flattened butterfly: a cost-efficient topology for high-radix networks," in Proc. of the 34th annual Intl. Symp. on Computer Architecture, 2007.
15. J. Liu, L.-R. Zheng, and H. Tenhunen, "A guaranteed-throughput switch for network-on-chip," in Proc. of the Intl. Symp. on System- on-Chip, 2003.
16. Z. Lu, M. Zhong, and A. Jantsch, "Evaluation of on-chip networks using deflection routing," in Proc. of the 16th ACM Great Lakes symp. on VLSI, 2006.
17. G. Michelogiannakis, J. Balfour, and W. J. Dally, "Elastic buffer flow control for on-chip networks," in Proc. of the 15th Intl. Symp. on High-Performance Computer Architecture, 2009.
18. T. Moscibroda and O. Mutlu, "A case for bufferless routing in on-chip networks," in Proc. of the 36th annual Intl. Symp. on Computer Architecture, 2009.
19. C. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M. S. Yousif, and C. R. Das, "ViChaR: A dynamic virtual channel regulator for network-on-chip routers," in Proc. of the 39th annual Intl. Symp. on Microarchitecture, 2006.
20. C. Nicopoulos, A. Yanamandra, S. Srinivasan, V. Narayanan, and M. J. Irwin, "Variation-aware low-power buffer design," in Proc. of The Asilomar Conf. on Signals, Systems, and Computers, 2007.
21. L.-S. Peh and W. J. Dally, "A delay model and speculative architecture for pipelined routers," in Proc. of the 7th Intl. Symp. on High-Performance Computer Architecture, 2001.
22. D. Sanchez, G. Michelogiannakis, and C. Kozyrakis, "An analysis of interconnection networks for large scale chip-multiprocessors," ACM Trans. on Arch. and Code Opt., vol. 7, no. 1, 2010.
23. H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik, "Orion: a power-performance simulator for interconnection networks," in Proc. of the 35th annual ACM/IEEE Intl. Symp. on Microarchitecture, 2002.
24. H. Wang, L.-S. Peh, and S. Malik, "Power-driven design of router microarchitectures in on-chip networks," in Proc. of the 36th annual IEEE/ACM Intl. Symp. on Microarchitecture, 2003.