Elastic-buffer flow control for on-chip networks

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 151-162

  Michelogiannakis, George ^a   Balfour, James ^a   Dally, William J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; FLOW CONTROL;

ADAPTIVE LOAD BALANCING; CHANNEL OCCUPANCY; CONTROL SCHEMES; DEADLOCK PREVENTION; MICRO ARCHITECTURES; ON-CHIP NETWORKS; PHYSICAL CHANNELS; VIRTUAL CHANNELS;

COMPUTER ARCHITECTURE;

EID: 64949139014     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798250     Document Type: Conference Paper

References (21)

1. James Balfour and William J. Dally. Design tradeoffs for tiled CMP on-chip networks. In ICS '06: Proceedings of the 20th annual International Conference on Supercomputing, pages 187-198, 2006.
2. T. Bjerregaard and S. Mahadevan. A survey of research and practices of network-on-chip. ACM Computing Surveys, 38(1):1, 2006.
3. William J. Dally. Virtual-channel flow control. IEEE Transactions on Parallel and Distributed Systems, 3(2):194-205, 1992.
4. William J. Dally and Hiromichi Aoki. Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Transanctions on Parallel and Distributed Systems, 4(4):466-475, 1993.
5. William J. Dally and Brian Towles. Route packets, not wires: On-chip interconnection networks. In DAC '01: Proceedings of the 38th Conference on Design Automation, pages 684- 689, 2001.
6. William J. Dally and Brian Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2003.
7. Giovanni de Micheli and Luca Benini. Networks on chip: A new paradigm for systems on chip design. In DATE '02: Proceedings of the conference on Design, Automation and Test in Europe, page 418, 2002.
8. Mike Galles. Spider: A high-speed network interconnect. IEEE Micro, 17(1):34-39, 1997.
9. Andreas Hansson, Kees Goossens, and Andrei Rǎdulescu. Avoiding message-dependent deadlock in network-based systems on chip. VLSI Design, May 2007.
10. Ron Ho, Ken Mai, and Mark Horowitz. Efficient on-chip global interconnects. In Symposium on VLSI Circuits, pages 271-274, 2003.
11. John Kim, William J. Dally, and Dennis Abts. Flattened butterfly: a cost-efficient topology for high-radix networks. In ISCA '07: Proceedings of the 34th annual International Symposium on Computer Architecture, pages 126-137, 2007.
12. Jong H. Kim, Ziqiang Liu, and Andrew A. Chien. Compressionless routing: a framework for adaptive and fault-tolerant routing. SIGARCH Computer Architecture News, 22(2):289-300, 1994.
13. Avinash Kodi, Ashwini Sarathy, and Ahmed Louri. Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. In ANCS '07: Proceedings of the 3rd ACM/IEEE Symposium on Architecture for Networking and Communications Systems, pages 47-56, 2007.
14. Jian Liu, Li-Rong Zheng, and H. Tenhunen. A guaranteedthroughput switch for network-on-chip. In Proceedings of International Symposium on System-on-Chip, pages 31-34, 2003.
15. Masayuki Mizuno, , William J. Dally, and Hideaki Onishi. Elastic interconnects: repeater-inserted long wiring capable of compressing and decompressing data. In ISSCC '01: Proceedings of IEEE International Solid-State Circuits Conference, pages 346-347, 464, 2001.
16. Robert Mullins, Andrew West, and Simon Moore. Lowlatency virtual-channel routers for on-chip networks. In ISCA '04: Proceedings of the 31st annual International Symposium on Computer Architecture, page 188, 2004.
17. Erland Nilsson, Mikael Millberg, Johnny Oberg, and Axel Jantsch. Load distribution with the proximity congestion awareness in a network on chip. In DATE '03: Proceedings of the conference on Design, Automation and Test in Europe, pages 1126-1127, 2003.
18. Arjun Singh. Load-Balanced Routing in Interconnection Networks. PhD in electrical engineering, Stanford University, 2005.
19. Vladimir Stojanovic and Vojin G. Oklobdzija. Comparative analysis of master-slave latches and flip-flops for highperformance and low-power systems. IEEE Journal of Solid-State Circuits, 34(4):536-548, Apr 1999.
20. Yoshio Turner and Yuval Tamir. Deadlock-free connectionbased adaptive routing with dynamic virtual circuits. Journal of Parallel and Distributed Computing, 67(1):13-32, 2007.
21. Daniel Wiklund and Dake Liu. SoCBUS: Switched networkon- chip for hard real time embedded systems. In IPDPS '03: Proceedings of the 17th International Symposium on Parallel and Distributed Processing, page 78.1, 2003.