Low-cost router microarchitecture for on-chip networks

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 255-266

  Kim, John ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Complexity; On chip network; Router microarchitecture

Indexed keywords

DESIGN COMPLEXITY; HIGH BANDWIDTH; INTERMEDIATE BUFFERS; LOW LATENCY; MICRO ARCHITECTURES; MULTI-CORE PROCESSOR; OFF-CHIP; ON-CHIP NETWORKS; POWER CONSUMPTION;

COST REDUCTION; EMBEDDED SYSTEMS;

ROUTERS;

EID: 76749128509     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669145     Document Type: Conference Paper

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