Row-based power-gating: A novel sleep transistor insertion methodology for leakage power optimization in nanometer CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 3, 2011, Pages 469-482

  Sathanur, Ashoka ^a   Benini, Luca ^b   Macii, Alberto ^a   Macii, Enrico ^a   Poncino, Massimo ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Leakage power; logic synthesis; low power design; power gating; power optimization

Indexed keywords

LEAKAGE POWER; LOGIC SYNTHESIS; LOW-POWER DESIGN; POWER GATING; POWER OPTIMIZATION;

CLUSTERING ALGORITHMS; CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; OPTIMIZATION; SLEEP RESEARCH; TIMING CIRCUITS; TRANSISTORS;

LEAKAGE CURRENTS;

EID: 79952039871     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2035448     Document Type: Article

References (28)

1. F. Fallah and M. Pedram, "Standby and active leakage current control and minimization in CMOS VLSI circuits," IEICE Trans. Electron., vol. E88-C, no. 4, pp. 509-519, Apr. 2005.
2. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOScircuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003. (Pubitemid 43779250)
3. V. Khandelwal and A. Srivastava, "Leakage control through fine-grained placement and sizing of sleep transistors," in Proc. IEEE/ACM Int. Conf. CAD (ICCAD), San Jose, CA, Nov. 2004, pp. 533-536. (Pubitemid 40449284)
4. M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual: For System-on-Chip Design. New York: Springer, 2007.
5. H. Jiang, M. Marek-Sadowska, and S. R. Nassif, "Benefits and costs of power-gating technique," in Proc. IEEE Int. Conf. Comput. Des. (ICCD), San Jose, CA, Oct. 2005, pp. 559-566. (Pubitemid 44362444)
6. S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, and T. Kaneko, "1-V power supply high-speed digital circuit technology with multithreshold voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
7. J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor sizing issues and tool for multi-threshold CMOS technology," in Proc. ACM/IEEE Des. Autom. Conf. (DAC), Anaheim, CA, Jun. 1997, pp. 409-414.
8. J. Kao, A. Chandrakasan, and S. Narendra, "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," in Proc. ACM/ IEEE Des. Autom. Conf. (DAC), San Francisco, CA, Jun. 1998, pp. 495-500.
9. M. Anis, S. Areibi, and M. Elmasry, "Design and optimization of multithreshold CMOS (MTCMOS) circuits," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 10, pp. 1324-1342, Oct. 2003.
10. M. Anis, S. Areibi, S. Mahmoud, and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," in Proc. ACM/IEEE Des. Autom. Conf. (DAC), New Orleans, LA, Jun. 2002, pp. 480-485.
11. W.Wang, M. Anis, and S. Areibi, "Fast techniques for standby leakage reduction in MTCMOS circuits," in Proc. IEEE Syst.-on-Chip Conf. (SOCC), Santa Clara, CA, Sep. 2004, pp. 21-24. (Pubitemid 40338351)
12. A. Ramalingam, B. Zhang, A. Devgan, and D. Z. Pan, "Sleep transistor sizing using timing criticality and temporal currents," in Proc. ACM/IEEE Asia-South Pacific Des. Autom. Conf. (ASPDAC), Shanghai, China, Jan. 2005, pp. 1094-1097.
13. C. Long and L. He, "Distributed sleep transistor network for power reduction," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp. 937-946, Sep. 2004.
14. D. S. Chiou, S. H. Chen, S. C. Chang, and C. Yeh, "Timing driven power gating," in Proc. ACM/IEEE Des. Autom. Conf. (DAC), San Francisco, CA, Jul. 2006, pp. 121-124. (Pubitemid 47113880)
15. D.-S. Chiou, D.-C. Juan, Y.-T. Chen, and S.-C. Chang, "Fine-grained sleep transistor sizing algorithm for leakage power minimization," in Proc. ACM/IEEE Des. Autom. Conf. (DAC), San Diego, CA, Jun. 2007, pp. 81-86. (Pubitemid 47129930)
16. T.-W. Chang, T.-T. Hwang, and S.-Y. Hsu, "Functionality directed clustering for low power MTCMOS design," in Proc. ACM/IEEE Asia-South Pacific Des. Autom. Conf. (ASPDAC), Shanghai, China, Jan. 2005, pp. 862-867.
17. C. Long, J. Xiong, and L. He, "On optimal physical synthesis of sleep transistors," in Proc. Int. Symp. Phys. Des. (ISPD), Phoenix, AZ, Apr. 2004, pp. 156-161.
18. P. Babighian, L. Benini, A. Macii, and E. Macii, "Post-layout leakage power minimization based on distributed sleep transistor insertion," in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des. (ISLPED), Newport Beach, CA, Aug. 2004, pp. 138-143. (Pubitemid 40454699)
19. K. Shi, Z. Lin, Y.-M. Jiang, and L.Yuan, "Simultaneous sleep transistor insertion and power network synthesis for industrial power gating designs," J. Comput., vol. 3, no. 3, pp. 6-13, Mar. 2008.
20. K. Usami and M. Horowitz, "Clustered voltage scaling technique for low-power design," in Proc. IEEE Int. Symp. Low Power Des. (ISLPD), Napa Valley, CA, Aug. 1995, pp. 3-8.
21. K. Usami, N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa, "Automated selective multi-threshold design for ultra-low standby applications," in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des. (ISLPED), Monterey, CA, Aug. 2002, pp. 202-206.
22. F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Kyoto, Japan, Jun. 1985, pp. 663-698.
23. A. Sathanur, A. Calimera, L. Benini, A. Macii, E. Macii, and M. Poncino, "Efficient computation of discharge current upper bounds for clustered sleep transistor sizing," in Proc. IEEE Des. Autom. Test Eur. (DATE), Nice, France, Apr. 2007, pp. 1-6.
24. A. Sathanur, A. Pullini, L. Benini, A. Macii, E. Macii, and M. Poncino, "Timing driven row-based power-gating," in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des. (ISLPED), Portland, OR, Aug. 2007, pp. 104-109.
25. F. S. Hillier and G. J. Lieberman, Introduction to Operations Research, 8th ed. New York: McGraw-Hill, 2005.
26. P. Babighian, L. Benini, A. Macii, and E. Macii, "Enabling fine-grain leakage management by voltage anchor insertion," in Proc. IEEE Des. Autom. Test Eur. (DATE), Munich, Germany, Mar. 2006, pp. 868-873.
27. A. Calimera, A. Pullini, A. Sathanur, L. Benini, A. Macii, E. Macii, and M. Poncino, "Design of a family of sleep transistor cells for a clustered power-gating flow in 65 nm technology," in Proc. ACM/IEEE Great Lakes Symp. VLSI (GLSVLSI), Stresa, Italy, Mar. 2007, pp. 501-504. (Pubitemid 47469787)
28. F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Portland, OR, May 1989, pp. 1929-1934. (Pubitemid 20665296)