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Volumn , Issue , 2004, Pages 156-161

On optimal physical synthesis of sleep transistors

Author keywords

Physical design; Power gating; Sleep transistors

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONSTRAINT THEORY; GATES (TRANSISTOR); MATHEMATICAL MODELS; PROBLEM SOLVING;

EID: 2942682812     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/981066.981101     Document Type: Conference Paper
Times cited : (18)

References (13)
  • 2
    • 0031639695 scopus 로고    scopus 로고
    • MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
    • J. Kao, S. Narendra, and A. Chandrakasan, "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," in DAC, 1998.
    • (1998) DAC
    • Kao, J.1    Narendra, S.2    Chandrakasan, A.3
  • 3
    • 0036049095 scopus 로고    scopus 로고
    • Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
    • M. Anis, S. Areibi, and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," in DAC, 2002.
    • (2002) DAC
    • Anis, M.1    Areibi, S.2    Elmasry, M.3
  • 4
    • 0042090410 scopus 로고    scopus 로고
    • Distributed sleep transistor network for power reduction
    • C. Long and L. He, "Distributed sleep transistor network for power reduction," in Proc. Design Automation Conf, pp. 181-186, 2003.
    • (2003) Proc. Design Automation Conf , pp. 181-186
    • Long, C.1    He, L.2
  • 6
    • 2942640758 scopus 로고    scopus 로고
    • On optimal physical synthesis of sleep transistors
    • EE Dept., UCLA
    • C. Long, J. Xiong, and L. He, "On optimal physical synthesis of sleep transistors," in Technical report, EE Dept., UCLA, 2003.
    • (2003) Technical Report
    • Long, C.1    Xiong, J.2    He, L.3
  • 7
    • 0032643254 scopus 로고    scopus 로고
    • Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings
    • X. D. Tan and C. J. Shi, "Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings," in Proc. Design Automation Conf, pp. 78-83, 1999.
    • (1999) Proc. Design Automation Conf , pp. 78-83
    • Tan, X.D.1    Shi, C.J.2
  • 8
    • 0027004894 scopus 로고
    • Power and ground network topology optimization for cell based VLSIs
    • T. Mitsuhashi and E. Kuh, "Power and ground network topology optimization for cell based VLSIs," in Proc. Design Automation Conf, pp. 524-529, 1992.
    • (1992) Proc. Design Automation Conf , pp. 524-529
    • Mitsuhashi, T.1    Kuh, E.2
  • 11
    • 2942671144 scopus 로고    scopus 로고
    • Automatic synthesis of power gating capable power/ground network
    • EE Dept., UCLA
    • C. Long, J. Xiong, and L. He, "Automatic synthesis of power gating capable power/ground network," in Technical report, EE Dept., UCLA, 2003.
    • (2003) Technical Report
    • Long, C.1    Xiong, J.2    He, L.3
  • 12
    • 84862368952 scopus 로고    scopus 로고
    • http://www.cbl.ncsu.edu.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.