Simultaneous sleep transistor insertion and power network synthesis for industrial power gating designs

Journal of Computers

Volumn 3, Issue 3, 2008, Pages 6-13

  Shi, Kaijian ^a   Lin, Zhian ^a   Jian, Yi Min ^a   Yuan, Lin ^a  

^a SYNOPSYS INC   (United States)

Author keywords

Algorithm; Low power; Method; P G network synthesis; Power gating; Sleep transistor; Switch cell

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER TRANSMISSION NETWORKS; LOW POWER ELECTRONICS; SLEEP RESEARCH;

LOW POWER; METHOD; NETWORK SYNTHESIS; POWER GATINGS; SLEEP TRANSISTORS;

TRANSISTORS;

EID: 77954873889     PISSN: 1796203X     EISSN: None     Source Type: Journal    
DOI: 10.4304/jcp.3.3.6-13     Document Type: Article

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