Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 501-504

  Calimera, Andrea ^a   Pullini, Antonio ^a   Sathanur, Ashoka Visweswara ^a   Benini, Luca ^b   MacIi, Alberto ^a   MacIi, Enrico ^a   Poncino, Massimo ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Insertion; Layout; Leakage power; Sleep transistor; Standard cell

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; NANOELECTRONICS; OPTIMIZATION;

AUTOMATED DESIGN FLOW; INSTANTIATION; POWER GATING INSERTION FLOW; SLEEP TRANSISTORS;

TRANSISTORS;

EID: 34748903744     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228903     Document Type: Conference Paper

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