Functionality directed clustering for low power MTCMOS design

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 862-867

  Chang, Tsuang Wei ^a   Hwang, Ting Ting ^a   Hsu, Sheng Yn ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC POWER UTILIZATION; GATES (TRANSISTOR); SLEEP RESEARCH; TOPOLOGY; TRANSISTORS;

CIRCUIT PERFORMANCE; DISCHARGE PATTERNS; DYNAMIC POWER CONSUMPTION; LEAKAGE POWER CONSUMPTION; MTCMOS CIRCUITS; MULTI-THRESHOLD CMOS; PERFORMANCE DEGRADATION; SLEEP TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 34548367377     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1121056     Document Type: Conference Paper

References (7)

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2. Mohab Anis. Shawki Areibi, Mohamed Mahmoud, and Mohamed Elmasry. "Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique," Proceedings of the 39th conference on Design automation, pp. 480-485, 2002.
3. Slickhar Borkar, "Low Power Challenges for the Decade", Proceedings of ASP-DAC. pp. 293-296, 2001
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6. J.Kao. A.Chandrakasan, and D.Antoniadis, "Transistor Sizing Issues and Tool for Multi-threshold CMOS Technology," Proceedings of the 34th conference on Design automation, pp. 409-414, 1997.
7. Harish Kriplani, Farid N. Najm. Ibrahim N. Hajj, " Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 998-1012, 1995