메뉴 건너뛰기




Volumn E88-C, Issue 4, 2005, Pages 509-519

Standby and active leakage current control and minimization in CMOS VLSI circuits

Author keywords

Leakage; Power; Sleep mode; Standby; Subthreshold

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; SWITCHING; TRANSISTORS; VLSI CIRCUITS;

EID: 28444449755     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e88-c.4.509     Document Type: Article
Times cited : (227)

References (39)
  • 3
    • 0001294031 scopus 로고    scopus 로고
    • Run-time power control scheme using software feedback loop for low-power real-time applications
    • Jan.
    • S. Lee and T. Sakurai, "Run-time power control scheme using software feedback loop for low-power real-time applications," Proc. Asia-Pacific Design Automation Conf., pp.381-386, Jan. 2000.
    • (2000) Proc. Asia-Pacific Design Automation Conf. , pp. 381-386
    • Lee, S.1    Sakurai, T.2
  • 4
    • 0034848830 scopus 로고    scopus 로고
    • Low-energy intra-task voltage scheduling using static timing analysis
    • June
    • D. Shin, J. Kim, and S. Lee, "Low-energy intra-task voltage scheduling using static timing analysis," Proc. Design Automation Conf., pp.438-443, June 2001.
    • (2001) Proc. Design Automation Conf. , pp. 438-443
    • Shin, D.1    Kim, J.2    Lee, S.3
  • 5
    • 3042560044 scopus 로고    scopus 로고
    • Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times
    • Feb.
    • K. Choi, R. Soma, and M. Pedram, "Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times," Proc. Design Automation and Test in Europe, vol.1, p. 10004, Feb. 2004.
    • (2004) Proc. Design Automation and Test in Europe , vol.1 , pp. 10004
    • Choi, K.1    Soma, R.2    Pedram, M.3
  • 6
    • 0031212817 scopus 로고    scopus 로고
    • Supply and threshold voltage scaling for low power CMOS
    • Aug.
    • R. Gonzalez, B. Gordon, and M. Horowitz, "Supply and threshold voltage scaling for low power CMOS," IEEE J. Solid-State Circuits, vol.32, no.8, pp.1210-1216, Aug. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , Issue.8 , pp. 1210-1216
    • Gonzalez, R.1    Gordon, B.2    Horowitz, M.3
  • 11
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • July-Aug.
    • S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol.19, no.4, pp.23-29, July-Aug. 1999.
    • (1999) IEEE Micro , vol.19 , Issue.4 , pp. 23-29
    • Borkar, S.1
  • 13
    • 0023401686 scopus 로고
    • BSIM: Berkeley short-channel IGFET model for MOS transistors
    • Aug.
    • B. Sheu, D. Scharfetter, P. Ko, and M. Jeng, "BSIM: Berkeley short-channel IGFET model for MOS transistors," IEEE J. Solid-State Circuits, vol.22, no.4, pp.558-566, Aug. 1987.
    • (1987) IEEE J. Solid-state Circuits , vol.22 , Issue.4 , pp. 558-566
    • Sheu, B.1    Scharfetter, D.2    Ko, P.3    Jeng, M.4
  • 14
  • 15
    • 0034230287 scopus 로고    scopus 로고
    • Dual-threshold voltage techniques for low-power digital circuits
    • July
    • J.T. Kao and A.P. Chandrakasan, "Dual-threshold voltage techniques for low-power digital circuits," IEEE J. Solid-State Circuits, vol.35, no.7, pp.1009-1018, July 2000.
    • (2000) IEEE J. Solid-state Circuits , vol.35 , Issue.7 , pp. 1009-1018
    • Kao, J.T.1    Chandrakasan, A.P.2
  • 16
    • 0031639695 scopus 로고    scopus 로고
    • MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
    • June
    • J. Kao, S. Narendra, and A. Chandrakasan, "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," Proc. Design Automation Conference, pp.495-500, June 1998.
    • (1998) Proc. Design Automation Conference , pp. 495-500
    • Kao, J.1    Narendra, S.2    Chandrakasan, A.3
  • 17
    • 0036049095 scopus 로고    scopus 로고
    • Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
    • June
    • M. Anis, S. Areibi, and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," Proc. Design Automation Conference, pp.480-485, June 2002.
    • (2002) Proc. Design Automation Conference , pp. 480-485
    • Anis, M.1    Areibi, S.2    Elmasry, M.3
  • 19
    • 0012109789 scopus 로고    scopus 로고
    • MTCMOS sequential circuits
    • J. Kao and A. Chandrakasan, "MTCMOS sequential circuits," Proc. ESSCIRC, pp.332-339, 2001.
    • (2001) Proc. ESSCIRC , pp. 332-339
    • Kao, J.1    Chandrakasan, A.2
  • 20
    • 0031162017 scopus 로고    scopus 로고
    • A 1-V high-speed MTCMOS circuit scheme for power-down application circuits
    • June
    • S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits," IEEE J. Solid-State Circuits, vol.32, no. 10, pp.861-870, June 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , Issue.10 , pp. 861-870
    • Shigematsu, S.1    Mutoh, S.2    Matsuya, Y.3    Tanabe, Y.4    Yamada, J.5
  • 28
    • 0033688763 scopus 로고    scopus 로고
    • Low power and high performance design challenges in future technologies
    • V. De and S. Borkar, "Low power and high performance design challenges in future technologies," Proc. 10th Great Lakes Symposium on VLSI, pp.1-6, 2000.
    • (2000) Proc. 10th Great Lakes Symposium on VLSI , pp. 1-6
    • De, V.1    Borkar, S.2
  • 29
    • 0000957831 scopus 로고    scopus 로고
    • Variable threshold-voltage CMOS technology
    • Nov.
    • T. Kuroda, T. Fujita, F. Hatori, and T. Sakurai, "Variable threshold-voltage CMOS technology," IEICE Trans. Electron., vol.E83-C, no.11, pp.1705-1715, Nov. 2000.
    • (2000) IEICE Trans. Electron. , vol.E83-C , Issue.11 , pp. 1705-1715
    • Kuroda, T.1    Fujita, T.2    Hatori, F.3    Sakurai, T.4
  • 31
    • 0032667127 scopus 로고    scopus 로고
    • Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
    • June
    • L. Wei, Z. Chen, K. Roy, Y. Ye, and V. De, "Mixed-Vth (MVT) CMOS circuit design methodology for low power applications," Proc. Design Automation Conference, pp.430-435, June 1999.
    • (1999) Proc. Design Automation Conference , pp. 430-435
    • Wei, L.1    Chen, Z.2    Roy, K.3    Ye, Y.4    De, V.5
  • 36
    • 33645579750 scopus 로고    scopus 로고
    • Minimizing leakage current in VLSI circuits
    • Department of Electrical Engineering, University of Southern California, May
    • A. Abdollahi, F. Fallah, and M. Pedram, "Minimizing leakage current in VLSI circuits," Technical Report, Department of Electrical Engineering, University of Southern California, no.02-08, May 2002.
    • (2002) Technical Report , Issue.2 , pp. 08
    • Abdollahi, A.1    Fallah, F.2    Pedram, M.3
  • 38
    • 0032640861 scopus 로고    scopus 로고
    • Leakage control with efficient use of transistor stacks in single threshold CMOS
    • June
    • M.C. Johnson, D. Somasekhar, and K. Roy, "Leakage control with efficient use of transistor stacks in single threshold CMOS," Proc. Design Automation Conference, pp.442-445, June 1999.
    • (1999) Proc. Design Automation Conference , pp. 442-445
    • Johnson, M.C.1    Somasekhar, D.2    Roy, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.