Sleep transistor sizing using timing criticality and temporal currents

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 1094-1097

  Ramalingam, Anand ^a   Zhang, Bin ^a   Devgan, Anirudh ^b   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; CRITICALITY (NUCLEAR FISSION); LOW POWER ELECTRONICS; SLEEP RESEARCH; TIMING CIRCUITS;

AREA REDUCTION; CIRCUIT TECHNIQUES; CLUSTER-BASED; CURRENT ESTIMATION; LOW-POWER OPERATION; POWER GATINGS; SLEEP TRANSISTORS; STATIC TIMING ANALYZERS;

TRANSISTORS;

EID: 84861447641     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120832     Document Type: Conference Paper

References (7)

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