Efficient computation of discharge current upper bounds for clustered sleep transistor sizing

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1544-1549

  Sathanur, A ^a   Calimera, A ^a   Benini, L ^b   Macii, A ^a   Macii, E ^a   Poncino, M ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATION THEORY; ELECTRIC DISCHARGES;

SCALABLE ALGORITHM; SPEED DEGRADATION; TIMING CONSTRAINTS;

TRANSISTORS;

EID: 34548356660     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364520     Document Type: Conference Paper

References (10)

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10. T.W. Chang et al. "Functionality directed clustering for low power MTCMOS design," 10th ASPDAC, pp. 862-867, 2005.