Fine-grained sleep transistor sizing algorithm for leakage power minimization

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 81-86

  Chiou, De Shiuan ^a   Juan, Da Cheng ^a   Chen, Yu Ting ^a   Chang, Shih Chieh ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

IR drop; Leakage current; Power gating

Indexed keywords

ALGORITHMS; INFRARED RADIATION; LEAKAGE CURRENTS; OPTIMIZATION;

DISTRIBUTED SLEEP TRANSISTOR NETWORK DESIGNS; FINE-GRAINED; MAXIMUM INSTANTANEOUS CURRENT; POWER GATING;

TRANSISTORS;

EID: 34547287213     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375129     Document Type: Conference Paper

References (15)

1. M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, "Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique," Proc. of the DAC, pp. 480-485, 2002.
2. D. S. Chiou, S. H. Chen, S. C. Chang, and C. Yeh, "Timing Driven Power Gating," Proc. of the DAC, pp. 121-124, 2006.
3. H. Chang and S. S. Sapatnekar, "Full-Chip Analysis of Leakage Power Under Process Variations, Including Spatial Correlations," Proc. of the DAC, pp. 523-528, 2005.
4. C. T. Hsieh, J. C. Lin, and S. C. Chang, "A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits," Proc. of ICCAD, pp. 537-540, 2004.
5. J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology," Proc. of the DAC, pp. 409-414, 1997.
6. J. Kao, S. Narendra, and A. Chandrakasan, "MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharging Patterns," Proc. of the DAC, pp. 495-500, 1998.
7. H. Kriplani, F. Najm, and I. N. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution," IEEE Transaction on CAD, vol. 14, no. 8, pp. 998-1012, Aug. 1995.
8. C. Long, and L. He, "Distributed Sleep Transistor Network for Power Reduction," IEEE Transaction on VLSI systems, vol. 12, no. 9, Sep. 2004.
9. S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, T. Kaneko, and J. Yamada, "A 1-V Multithreshold-Voltage CMOS Digital Signal Processor for Mobile Phone Application," IEEE JSSC, vol. 31, no. 11, Nov. 1996.
10. R. R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, "Parametric Yield Estimation Considering Leakage Variability," Proc. of the DAC, pp. 442-447, 2004.
11. K. Roy, S. Mukhopadhyay and H. M. Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," Proc. of the IEEE, Feb. 2003.
12. K. Shi, and D. Howard, "Challenges in Sleep Transistor Design and Implementation in Low-Power Designs," Proc. of the DAC, pp. 113-116, 2006.
13. C. Y. Wang and K. Roy, "Maximization of power dissipation in large CMOS circuits considering spurious transitions," IEEE Transaction on Circuits and Systems, vol 47, no 4, pp. 483-490, Apr. 2000.
14. W. Wang, M. Anis, and S. Areibi, "Fast Techniques for Standby Leakage Reduction in MTCMOS Circuits," Proc. of the IEEE International SOCC, pp. 21-24, 2004.
15. Synopsys Inc. PrimePower Version-X 2005, 12 - User's Manual.