-
1
-
-
0036049095
-
Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique
-
th DAC, pp. 480-485, 2002.
-
(2002)
th DAC
, pp. 480-485
-
-
Anis, M.1
and et, al.2
-
2
-
-
16244387662
-
A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits
-
Hsieh, C. T., Lin, J. C., and Chang, S. C., "A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits," Proc. of ICCAD, pp. 537-540, 2004.
-
(2004)
Proc. of ICCAD
, pp. 537-540
-
-
Hsieh, C.T.1
Lin, J.C.2
Chang, S.C.3
-
3
-
-
0030655539
-
Estimation of Maximum Power and Instantaneous Current using a Genetic Algorithm
-
Jiang, Y.M., and et al., "Estimation of Maximum Power and Instantaneous Current using a Genetic Algorithm," Proc. of the Custom Integrated Circuits Conf, pp. 135-138, 1997.
-
(1997)
Proc. of the Custom Integrated Circuits Conf
, pp. 135-138
-
-
Jiang, Y.M.1
and et, al.2
-
4
-
-
0030672649
-
Vector Generation for Maximum Instantaneous Current through Supply Lines for CMOS Circuits
-
th DAC, pp. 383-388, 1997.
-
(1997)
th DAC
, pp. 383-388
-
-
Kristic, A.1
Cheng, K.T.2
-
5
-
-
0030697754
-
Transistor Sizing Issues and Tool for Multi-threshold CMOS Technology
-
th DAC, pp. 409-414, 1997.
-
(1997)
th DAC
, pp. 409-414
-
-
Kao, J.1
and et, al.2
-
7
-
-
0036907029
-
Subthreshold leakage modeling and reduction techniques
-
Kao, J., and et al., "Subthreshold leakage modeling and reduction techniques," Proc. of ICCAD, pp. 141-148, 2002.
-
(2002)
Proc. of ICCAD
, pp. 141-148
-
-
Kao, J.1
and et, al.2
-
8
-
-
0042090410
-
Distributed Sleep Transistor Network for Power Reduction
-
th DAC, pp. 181-186, 2003.
-
(2003)
th DAC
, pp. 181-186
-
-
Long, C.1
He, L.2
-
9
-
-
0029359285
-
1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS
-
Aug
-
Mutoh, S., and et al, "1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS," IEEE JSSC, vol. 30, no. 8, pp. 847-854, Aug. 1995.
-
(1995)
IEEE JSSC
, vol.30
, Issue.8
, pp. 847-854
-
-
Mutoh, S.1
and et, al.2
-
10
-
-
33646864552
-
Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits
-
Feb
-
Roy, K., Mukhopadhyay, S., and Mahmoodi-Meimand, H., "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," Proc. of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
-
(2003)
Proc. of the IEEE
, vol.91
, Issue.2
, pp. 305-327
-
-
Roy, K.1
Mukhopadhyay, S.2
Mahmoodi-Meimand, H.3
-
11
-
-
0032688692
-
Stand-by Power Minimization through Simultaneous Threshold Voltage Selection and Circuit Sizing
-
th DAC, pp.436-441, 1999.
-
(1999)
th DAC
, pp. 436-441
-
-
Sirichotiyakul, S.1
-
12
-
-
0242720765
-
Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors
-
Nov
-
Tschanz, J. W., and et al., "Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors," IEEE JSSC, vol. 38, no. 11, pp. 1838-1845, Nov. 2003.
-
(2003)
IEEE JSSC
, vol.38
, Issue.11
, pp. 1838-1845
-
-
Tschanz, J.W.1
and et, al.2
-
13
-
-
0033100297
-
Design and Optimization of Dual-Threshold Circuits for Low-Voltage Low-Power Applications
-
Mar
-
Wei, L., and et al., "Design and Optimization of Dual-Threshold Circuits for Low-Voltage Low-Power Applications," IEEE Transactions of VLSI Systems, vol. 7, no. 1, pp. 16-24, Mar. 1999.
-
(1999)
IEEE Transactions of VLSI Systems
, vol.7
, Issue.1
, pp. 16-24
-
-
Wei, L.1
and et, al.2
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