A 32 nm high-K metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 1, 2011, Pages 76-84

  Kolar, Pramod ^a   Karl, Eric ^a   Bhattacharya, Uddalak ^a   Hamzaoglu, Fatih ^a   Nho, Henry ^b   Ng, Yong Gee ^a   Wang, Yih ^a   Zhang, Kevin ^a  

^a INTEL CORPORATION   (United States)

^b LG Electronics Inc   (South Korea)

Author keywords

32 nm; CMOS memory integrated circuits; high k+metal gate; process variations; read assist; sram sensors; static random access memory (SRAM); systematic variation; Vccmin; word line under drive

Indexed keywords

32 NM; CMOS MEMORY INTEGRATED CIRCUITS; HIGH-K+METAL-GATE; PROCESS VARIATION; READ ASSIST; SRAM SENSORS; STATIC RANDOM ACCESS MEMORY; SYSTEMATIC VARIATION; VCCMIN; WORD-LINE UNDER-DRIVE;

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; SENSORS;

STATIC RANDOM ACCESS STORAGE;

EID: 78650921532     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2084490     Document Type: Conference Paper

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