Cache design for low power and high yield

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 103-107

  Mohammad, Baker ^a,b   Saint Laurent, Martin ^a   Bassett, Paul ^a   Abraham, Jacob ^b  

^a QUALCOMM INC   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; CACHE DESIGNS; CHIP AREAS; ELECTRONIC DESIGNS; HIGH YIELD; INTERNATIONAL SYMPOSIUM; LOW POWERS; LOW-VOLTAGE OPERATIONS; NEGATIVE BIAS- TEMPERATURE-INSTABILITY; NEW TECHNOLOGIES; NOISE MARGIN; ON CHIPS; OPERATING VOLTAGES; PARAMETRIC VARIATIONS; PROCESS VARIABILITY; SINGLE VOLTAGE SUPPLY; SOFTWARE CONTROLLABILITY; STATIC-NOISE MARGIN; SUPPLY VOLTAGES; VOLTAGE SWINGS;

CHLORINE COMPOUNDS; CMOS INTEGRATED CIRCUITS; ELECTRONICS ENGINEERING; NEGATIVE TEMPERATURE COEFFICIENT; NONMETALS; RADIOACTIVE MATERIALS; SILICON; TECHNOLOGY; THERMODYNAMIC STABILITY;

STATIC RANDOM ACCESS STORAGE;

EID: 49749117878     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479707     Document Type: Conference Paper

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