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Volumn 8, Issue 3, 2008, Pages 519-525

Effect of BTI degradation on transistor variability in advanced semiconductor technologies

Author keywords

Bias temperature instability (BTI); High k dielectrics; Metal gate; SRAM; Transistor reliability; Vccmin

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; GATES (TRANSISTOR); NEGATIVE TEMPERATURE COEFFICIENT; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; THERMODYNAMIC STABILITY; TRANSISTORS;

EID: 54949086382     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2008.2002351     Document Type: Article
Times cited : (74)

References (18)
  • 1
    • 33846061871 scopus 로고    scopus 로고
    • Erratic fluctuations of SRAM cache Vmin at the 90 nm process technology node
    • M. Agostinelli et al., "Erratic fluctuations of SRAM cache Vmin at the 90 nm process technology node," in IEDM Tech. Dig., 2005, pp. 655-658.
    • (2005) IEDM Tech. Dig , pp. 655-658
    • Agostinelli, M.1
  • 2
    • 46049093814 scopus 로고    scopus 로고
    • SRAM cell static noise margin and Vmin sensitivity to transistor degradation
    • A. Krishnan et al., "SRAM cell static noise margin and Vmin sensitivity to transistor degradation," in IEDM Tech. Dig., 2006, pp. 1-4.
    • (2006) IEDM Tech. Dig , pp. 1-4
    • Krishnan, A.1
  • 4
    • 41549168299 scopus 로고    scopus 로고
    • Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS
    • K. Kuhn, "Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS," in IEDM Tech. Dig., 2007, pp. 471-474.
    • (2007) IEDM Tech. Dig , pp. 471-474
    • Kuhn, K.1
  • 5
    • 0028571338 scopus 로고
    • Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits
    • D. Burnett et al., "Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits," in VLSI Symp. Tech. Dig., 1994, pp. 15-16.
    • (1994) VLSI Symp. Tech. Dig , pp. 15-16
    • Burnett, D.1
  • 6
    • 50249185641 scopus 로고    scopus 로고
    • A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging
    • K. Mistry et al., "A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging," in IEDM Tech. Dig., 2007, pp. 247-250.
    • (2007) IEDM Tech. Dig , pp. 247-250
    • Mistry, K.1
  • 7
    • 54949127466 scopus 로고    scopus 로고
    • Reliability challenges: Preventing them from becoming limiters to technology scaling
    • Invited talk
    • J. Maiz, "Reliability challenges: Preventing them from becoming limiters to technology scaling," in Proc. Int. Integr. Rel. Workshop, 2006. Invited talk.
    • (2006) Proc. Int. Integr. Rel. Workshop
    • Maiz, J.1
  • 8
    • 49549100226 scopus 로고    scopus 로고
    • Effect of BTI degradation on transistor variability in advanced logic technologies
    • S. Pae et al., "Effect of BTI degradation on transistor variability in advanced logic technologies," in Proc, Int. Integr. Rel. Workshop, 2007, pp. 18-21.
    • (2007) Proc, Int. Integr. Rel. Workshop , pp. 18-21
    • Pae, S.1
  • 9
    • 40549122135 scopus 로고    scopus 로고
    • Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation
    • Sep
    • A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M. A. Alam, "Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2143-2154, Sep. 2007.
    • (2007) IEEE Trans. Electron Devices , vol.54 , Issue.9 , pp. 2143-2154
    • Islam, A.E.1    Kufluoglu, H.2    Varghese, D.3    Mahapatra, S.4    Alam, M.A.5
  • 10
    • 0016538539 scopus 로고
    • Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics
    • Aug
    • R. Keyes, "Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics," IEEE J. Solid-State Circuits, vol. SSC-10, no. 4, pp. 245-247, Aug. 1975.
    • (1975) IEEE J. Solid-State Circuits , vol.SSC-10 , Issue.4 , pp. 245-247
    • Keyes, R.1
  • 11
    • 28744454913 scopus 로고    scopus 로고
    • Random charge effects for PMOS NBTI in ultra-small gate area devices
    • M. Agostinelli et al., "Random charge effects for PMOS NBTI in ultra-small gate area devices," in Proc. Int. Rel. Phys. Symp., 2005, pp. 529-532.
    • (2005) Proc. Int. Rel. Phys. Symp , pp. 529-532
    • Agostinelli, M.1
  • 12
    • 0041358085 scopus 로고    scopus 로고
    • T and β mismatch shifts in pMOSFETs
    • Dec
    • T and β mismatch shifts in pMOSFETs," IEEE Trans. Device Mater. Rel., vol. 2, no. 4, pp. 89-93, Dec. 2002.
    • (2002) IEEE Trans. Device Mater. Rel , vol.2 , Issue.4 , pp. 89-93
    • Rauch, S.1
  • 13
    • 37549047923 scopus 로고    scopus 로고
    • Review and reexamination of reliability effects related to NBTI-induced statistical variations
    • Dec
    • S. Rauch, "Review and reexamination of reliability effects related to NBTI-induced statistical variations," IEEE Trans. Device Mater. Rel., vol. 7, no. 4, pp. 524-530, Dec. 2007.
    • (2007) IEEE Trans. Device Mater. Rel , vol.7 , Issue.4 , pp. 524-530
    • Rauch, S.1
  • 15
    • 0041340533 scopus 로고    scopus 로고
    • Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing
    • Jul
    • D. K. Schroder et al., "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," J. Appl. Phys., vol. 94, no. 1, pp. 1-18, Jul. 2003.
    • (2003) J. Appl. Phys , vol.94 , Issue.1 , pp. 1-18
    • Schroder, D.K.1
  • 17
    • 51549107155 scopus 로고    scopus 로고
    • BTI reliability of 45 nm high-K + metal gate process technology
    • S. Pae et al., "BTI reliability of 45 nm high-K + metal gate process technology," in Proc. IRPS, 2008, pp. 352-357.
    • (2008) Proc. IRPS , pp. 352-357
    • Pae, S.1
  • 18
    • 3042561384 scopus 로고    scopus 로고
    • PMOS NBTI-induced circuit mismatch in advanced technologies
    • M. Agostinelli et al., "PMOS NBTI-induced circuit mismatch in advanced technologies," in Proc. Int. Rel. Phys. Symp., 2004, pp. 171-175.
    • (2004) Proc. Int. Rel. Phys. Symp , pp. 171-175
    • Agostinelli, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.