A 45nm 8-core enterprise xeon® processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 56-57

  Rusu, Stefan ^a   Tam, Simon ^a   Muljono, Harry ^a   Stinson, Jason ^a   Ayers, David ^a   Chang, Jonathan ^a   Varada, Raj ^a   Ratta, Matt ^a   Kottapalli, Sailesh ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349285149     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977305     Document Type: Conference Paper

References (3)

1. K. Mistry, C. Allten, C. Auth, et al., "A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", IEDM Dig. Tech. Papers, pp. 247-250, Dec. 2007.
2. F. Hamzaoglu, K. Zhang, Y. Wang, et al., "A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-K Metal-Gate CMOS Technology ", ISSCC Dig. Tech. Papers, pp. 376-377, Feb. 2008.
3. N. Kurd, J. Douglas, P. Mosalikanti, et al., "Next generation Intel® micro-architecture (Nehalem) clocking architecture", VLSI Circuits Symposium, pp. 62-63, Jun. 2008.