A minimum total power methodology for projecting limits on CMOS GSI

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 3, 2000, Pages 235-251

  Bhavnagarwala, Azeez J ^b   Austin, Blanca L ^b   Bowman, Keith A ^b   Meindl, James D ^a,b  

^a IEEE

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Low voltage CMOS; Minimum power CMOS; Voltage scaling

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC POWER SUPPLIES TO APPARATUS; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; TEMPERATURE; THRESHOLD VOLTAGE;

LOW VOLTAGE CMOS; MINIMUM POWER CMOS; SHORT CHANNEL THRESHOLD VOLTAGE ROLLOFF; SOFTWARE PACKAGE HSPICE; TOTAL POWER METHODOLOGY; VOLTAGE SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 0033722287     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.845891     Document Type: Article

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