A 4.0 GHz 291 Mb voltage-scalable SRAM design in a 32 nm high-k + metal-gate CMOS technology with integrated power management

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 1, 2010, Pages 103-110

  Wang, Yih ^a   Bhattacharya, Uddalak ^a   Hamzaoglu, Fatih ^a   Kolar, Pramod ^a   Ng, Yong Gee ^a   Wei, Liqiong ^a   Zhang, Ying ^a   Zhang, Kevin ^a   Bohr, Mark ^a  

^a INTEL CORPORATION   (United States)

Author keywords

32 nm; CMOS memory integrated circuits; High k + metal gate; Sleep transistor; Static random access memory (SRAM); Variations

Indexed keywords

ARRAY EFFICIENCY; BIT DENSITY; BIT LINES; BITCELL; CLOSE LOOP; CMOS MEMORY INTEGRATED CIRCUITS; CMOS TECHNOLOGY; EMBEDDED APPLICATION; HIGH FREQUENCY HF; INTEGRATED POWER MANAGEMENT; LEAKAGE CONTROL; LEAKAGE POWER; LEAKAGE POWER CONSUMPTION; LOW POWER; MEMORY ARRAY; METAL-GATE; OPERATING FREQUENCY; OPERATING VOLTAGE; SLEEP TRANSISTORS; SRAM DESIGN; STATIC RANDOM ACCESS MEMORY; SUBARRAY; SUPPLY VOLTAGES; WORDLINES;

ELECTRIC POWER MEASUREMENT; ENERGY MANAGEMENT; INTEGRATED CIRCUITS; LOGIC DESIGN; METALS; SLEEP RESEARCH; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 73249132942     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2034082     Document Type: Conference Paper

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