A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149μm2 cell in 32nm high-κ metal-gate CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 348-349

  Fujimura, Yuki ^a   Hirabayashi, Osamu ^a   Sasaki, Takahiko ^a   Suzuki, Azuma ^a   Kawasumi, Atsushi ^a   Takeyama, Yasuhisa ^a   Kushida, Keiichi ^a   Fukano, Gou ^a   Katayama, Akira ^a   Niki, Yusuke ^a   Yabe, Tomoaki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; CMOS TECHNOLOGY; CONFIGURABLE; CONVENTIONAL DESIGN; FAILURE RATE; LOW VOLTAGE OPERATION; MEASUREMENT RESULTS; MEMORY CELL; METAL-GATE; ORDERS OF MAGNITUDE; RISETIMES; TEST-CHIP; WORDLINES; WRITE MARGIN;

CMOS INTEGRATED CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 77952208436     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433813     Document Type: Conference Paper

References (4)

1. K. Nii et al., "A 45-nm Single-port and Dual-port SRAM family with Robust Read/Write Stabilizing Circuitry under DVFS Environment," Symp. VLSI Circuits, pp. 212-213, Jun. 2008.
2. Y. Wang et al., "A 4.0 GHz 291Mb Voltage-Scalable SRAM Design in 32nm High-κ Metal-Gate CMOS with Integrated Power Management," ISSCC Dig. Tech. Papers, pp. 456-457, Feb. 2009.
3. H.S. Yang et al., "Scaling of 32nm Low Power SRAM with High-κ Metal Gate," IEDM Dig. Tech. Papers, pp. 233-236, Dec. 2008.
4. 2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver," ISSCC Dig. Tech. Papers, pp. 458-459, Feb. 2009.