Interface-trap effects in inversion-type enhancement-mode InGaAs/ZrO 2 n-channel MOSFETs

IEEE Transactions on Electron Devices

Volumn 58, Issue 1, 2011, Pages 107-114

  Morassi, Luca ^a   Padovani, Andrea ^a   Verzellesi, Giovanni ^a   Veksler, Dmitry ^b   Ok, Injo ^b   Bersuker, Gennadi ^b  

^a UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^b SEMATECH   (United States)

Author keywords

High k dielectric; III V MOSFETs; InGaAs; interface traps; numerical simulation

Indexed keywords

HIGH-K DIELECTRIC; III-V MOSFETS; INGAAS; INTERFACE TRAPS; NUMERICAL SIMULATION;

COMPUTER SIMULATION; GALLIUM; GATE DIELECTRICS; GATES (TRANSISTOR); MATHEMATICAL MODELS; SEMICONDUCTING INDIUM; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 78650873807     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2086461     Document Type: Article

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