-
1
-
-
33748575889
-
Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovation
-
D. A. Antoniadis, I. Aberg, C. N. Chleirigh, O. M. Nayfeh, A. Khakifirooz, and J. L. Hoyt, "Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovation," IBM J. Res. Develop., vol. 50, no. 4/5, pp. 363-376, 2006.
-
(2006)
IBM J. Res. Develop
, vol.50
, Issue.4-5
, pp. 363-376
-
-
Antoniadis, D.A.1
Aberg, I.2
Chleirigh, C.N.3
Nayfeh, O.M.4
Khakifirooz, A.5
Hoyt, J.L.6
-
4
-
-
33847169809
-
-
0.3As HEMTs, in Proc. 18th IEEE IPRM Conf., May 2006, pp. 177-180.
-
0.3As HEMTs," in Proc. 18th IEEE IPRM Conf., May 2006, pp. 177-180.
-
-
-
-
5
-
-
35148860155
-
0.3As HEMTs for beyond-CMOS applications
-
Oct
-
0.3As HEMTs for beyond-CMOS applications," IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 2606-2613, Oct. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.10
, pp. 2606-2613
-
-
Kim, D.-H.1
del Alamo, J.A.2
Lee, J.-H.3
Seo, K.-S.4
-
7
-
-
0036803456
-
-
T of 562 GHz, IEEE Electron Device Lett., 23, no. 10, pp. 573-575, Oct. 2002.
-
T of 562 GHz," IEEE Electron Device Lett., vol. 23, no. 10, pp. 573-575, Oct. 2002.
-
-
-
-
8
-
-
0037672004
-
InP-based high electron mobility transistors with a very short gate-channel distance
-
Apr
-
A. Endoh, Y. Yamashita, K. Shinohara, K. Hikosaka, T. Matsui, S. Hiyamizu, and T. Minima, "InP-based high electron mobility transistors with a very short gate-channel distance," Jpn. J. Appl. Phys., vol. 42, no. 4B, pp. 2214-2218, Apr. 2003.
-
(2003)
Jpn. J. Appl. Phys
, vol.42
, Issue.4 B
, pp. 2214-2218
-
-
Endoh, A.1
Yamashita, Y.2
Shinohara, K.3
Hikosaka, K.4
Matsui, T.5
Hiyamizu, S.6
Minima, T.7
-
9
-
-
53649083855
-
Quantum-corrected Monte Carlo analysis of scaling behavior of nano-scale InGaAs high electron mobility transistors
-
Jul
-
H. I. Fujishiro, T. Kawabata, and J. A. del Alamo, "Quantum-corrected Monte Carlo analysis of scaling behavior of nano-scale InGaAs high electron mobility transistors," Phys. Stat. Sol. (C), vol. 5, no. 9, pp. 2795-2798, Jul. 2008.
-
(2008)
Phys. Stat. Sol. (C)
, vol.5
, Issue.9
, pp. 2795-2798
-
-
Fujishiro, H.I.1
Kawabata, T.2
del Alamo, J.A.3
-
11
-
-
0030085596
-
High-performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt-based buried-gate technologies
-
Feb
-
K. J. Chen, T. Enoki, K. Maezawa, K. Arai, and M. Yamamoto, "High-performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt-based buried-gate technologies," IEEE Trans. Electron Devices, vol. 43, no. 2, pp. 252-257, Feb. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, Issue.2
, pp. 252-257
-
-
Chen, K.J.1
Enoki, T.2
Maezawa, K.3
Arai, K.4
Yamamoto, M.5
-
12
-
-
23744462065
-
Nanogate InP-HEMT technology for ultrahigh-speed performance
-
K. Shinohara, Y. Yamashita, A. Endoh, I. Watanabe, K. Hikosaka, T. Minima, S. Hiyamizu, and T. Matsui, "Nanogate InP-HEMT technology for ultrahigh-speed performance," in Proc. 16th IEEE IPRM Conf., 2004, pp. 721-726.
-
(2004)
Proc. 16th IEEE IPRM Conf
, pp. 721-726
-
-
Shinohara, K.1
Yamashita, Y.2
Endoh, A.3
Watanabe, I.4
Hikosaka, K.5
Minima, T.6
Hiyamizu, S.7
Matsui, T.8
-
13
-
-
0032663797
-
High-performance 0.1-μm gate enhancement-mode InAlAs/InGaAs HEMTs using two-step recessed gate technology
-
Jun
-
T. Suemitsu, H. Yokoyama, Y. Umeda, T. Enoki, and Y. Ishii, "High-performance 0.1-μm gate enhancement-mode InAlAs/InGaAs HEMTs using two-step recessed gate technology," IEEE. Trans. Electron Devices, vol. 46, no. 6, pp. 1074-1080, Jun. 1999.
-
(1999)
IEEE. Trans. Electron Devices
, vol.46
, Issue.6
, pp. 1074-1080
-
-
Suemitsu, T.1
Yokoyama, H.2
Umeda, Y.3
Enoki, T.4
Ishii, Y.5
-
14
-
-
0001069003
-
Improved recessed-gate structure for sub-0.1-μm-gate InP-based high electron mobility transistors
-
Mar
-
T. Suemitsu, T. Enoki, H. Yokoyama, and Y. Ishii, "Improved recessed-gate structure for sub-0.1-μm-gate InP-based high electron mobility transistors," Jpn. J. Appl. Phys., vol. 37, no. 3B, pp. 1365-1372, Mar. 1998.
-
(1998)
Jpn. J. Appl. Phys
, vol.37
, Issue.3 B
, pp. 1365-1372
-
-
Suemitsu, T.1
Enoki, T.2
Yokoyama, H.3
Ishii, Y.4
-
15
-
-
34548480154
-
-
T.-W. Kim, D.-H. Kim, S. D. Park, J. W. Bae, G. Y. Yeom, J.-I. Song, and J. H. Jang, Fabrication of InAs composite channel high electron mobility transistors by utilizing Ne-based atomic layer etching, Appl. Phys. Lett., 91, no. 10, pp. 012110-1-012 110-3, Sep. 2007.
-
T.-W. Kim, D.-H. Kim, S. D. Park, J. W. Bae, G. Y. Yeom, J.-I. Song, and J. H. Jang, "Fabrication of InAs composite channel high electron mobility transistors by utilizing Ne-based atomic layer etching," Appl. Phys. Lett., vol. 91, no. 10, pp. 012110-1-012 110-3, Sep. 2007.
-
-
-
-
16
-
-
15844407150
-
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
-
Mar
-
R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, "Benchmarking nanotechnology for high-performance and low-power logic transistor applications," IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 153-158, Mar. 2005.
-
(2005)
IEEE Trans. Nanotechnol
, vol.4
, Issue.2
, pp. 153-158
-
-
Chau, R.1
Datta, S.2
Doczy, M.3
Doyle, B.4
Jin, B.5
Kavalieros, J.6
Majumdar, A.7
Metz, M.8
Radosavljevic, M.9
-
17
-
-
0030216180
-
Nonlinear source and drain resistance in recessed-gate heterostructure field-effect transistors
-
Aug
-
D. R. Greenberg and J. A. del Alamo, "Nonlinear source and drain resistance in recessed-gate heterostructure field-effect transistors," IEEE Trans. Electron Devices, vol. 43, no. 8, pp. 1304-1306, Aug. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, Issue.8
, pp. 1304-1306
-
-
Greenberg, D.R.1
del Alamo, J.A.2
-
18
-
-
0023294433
-
Relationship between measured and intrinsic transconductances of FETs
-
Feb
-
S. Y. Chou and D. A. Antoniadis, "Relationship between measured and intrinsic transconductances of FETs," IEEE Trans. Electron Devices vol. ED-34, no. 2, pp. 448-450, Feb. 1987.
-
(1987)
IEEE Trans. Electron Devices
, vol.ED-34
, Issue.2
, pp. 448-450
-
-
Chou, S.Y.1
Antoniadis, D.A.2
-
19
-
-
0026896303
-
Scaling the Si MOSFET: From bulk to SOI to bulk
-
Jul
-
R.-H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704-1710, Jul. 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.7
, pp. 1704-1710
-
-
Yan, R.-H.1
Ourmazd, A.2
Lee, K.F.3
-
20
-
-
0027847411
-
Scaling theory for double-gate SOI MOSFETs
-
Dec
-
K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, "Scaling theory for double-gate SOI MOSFETs," IEEE Trans. Electron Devices vol. 40, no. 12, pp. 2326-2329, Dec. 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, Issue.12
, pp. 2326-2329
-
-
Suzuki, K.1
Tanaka, T.2
Tosaka, Y.3
Horie, H.4
Arimoto, Y.5
-
21
-
-
33846611741
-
85 nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications
-
S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. J. Phillips, D. Wallis, P. Wilding, and R. Chau, "85 nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications," in IEDM Tech. Dig., 2005, pp. 763-766.
-
(2005)
IEDM Tech. Dig
, pp. 763-766
-
-
Datta, S.1
Ashley, T.2
Brask, J.3
Buckle, L.4
Doczy, M.5
Emeny, M.6
Hayes, D.7
Hilton, K.8
Jefferies, R.9
Martin, T.10
Phillips, T.J.11
Wallis, D.12
Wilding, P.13
Chau, R.14
-
22
-
-
33845988529
-
A 65 nm ultra low power logic platform technology using uni-axial strained silicon transistors
-
C.-H. Jan, P. Bai, J. Choi, G. Curello, S. Jacobs, J. Jeong, K. Johnson, D. Jones, S. Klopcic, J. Lin, N. Lindert, A. Lio, S. Natarajan, J. Neirynck, P. Packan, J. Park, I. Post, M. Patel, S. Ramey, P. Reese, L. Rockford, A. Roskowski, G. Sacks, B. Turkot, Y. Wang, L. Wei, J. Young, K. Zhang, Y. Zhang, M. Bohr, and B. Holt, "A 65 nm ultra low power logic platform technology using uni-axial strained silicon transistors," in IEDM Tech. Dig., 2005, pp. 60-63.
-
(2005)
IEDM Tech. Dig
, pp. 60-63
-
-
Jan, C.-H.1
Bai, P.2
Choi, J.3
Curello, G.4
Jacobs, S.5
Jeong, J.6
Johnson, K.7
Jones, D.8
Klopcic, S.9
Lin, J.10
Lindert, N.11
Lio, A.12
Natarajan, S.13
Neirynck, J.14
Packan, P.15
Park, J.16
Post, I.17
Patel, M.18
Ramey, S.19
Reese, P.20
Rockford, L.21
Roskowski, A.22
Sacks, G.23
Turkot, B.24
Wang, Y.25
Wei, L.26
Young, J.27
Zhang, K.28
Zhang, Y.29
Bohr, M.30
Holt, B.31
more..
-
23
-
-
33745695096
-
GATE CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2 nm gate oxide
-
GATE CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2 nm gate oxide," in IEDM Tech. Dig., 2005, pp. 227-230.
-
(2005)
IEDM Tech. Dig
, pp. 227-230
-
-
Rande, P.1
Ghani, T.2
Kuhn, K.3
Mistry, K.4
Pae, S.5
Shifren, L.6
Stettler, M.7
Tone, K.8
Tyagi, S.9
Bohr, M.10
|