Heterogeneous integration of enhancement mode in0.7Ga 0.3As quantum well transistor on silicon substrate using thin (≤ 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5V) logic applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 625-628

  Hudait, M K ^a   Dewey, G ^a   Datta, S ^a   Fastenau, J M ^b   Kavalieros, J ^a   Liu, W K ^b   Lubyshev, D ^b   Pillarisetty, R ^a   Rachmady, W ^a   Radosavljevic, M ^a   Rakshit, T ^a   Chau, Robert ^a  

^a INTEL CORPORATION   (United States)

^b IQE INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENHANCEMENT MODE; HETEROGENEOUS INTEGRATION;

ELECTRON DEVICES;

EID: 49149131108     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4419017     Document Type: Conference Paper

References (4)

1. S. Datta et al, IEEE Electron Dev. Lett., vol. 28 (8), p. 685 (2007).
2. D. Kim and J. A. del Alamo, IEDM Tech. Dig., p. 837 (2006).
3. Y. Yamashita et al, IEEE Electron Dev. Lett., vol. 23 (10), p. 573 (2002).
4. D. Lubyshev et al, J. Vac. Sci. Technol. B, vol. 22 (3), p. 1565 (2004).