High speed Cu filling into TSV by pulsed current for 3 dimensional chip stacking

Journal of Korean Institute of Metals and Materials

Volumn 48, Issue 7, 2010, Pages 667-673

  Kim, Rak ^a   Park, Jun Kyu ^a   Chu, Yang Cheol ^b   Jung, Jae Pil ^a  

^a University of Seoul   (South Korea)

^b Duksan Hi Metal Co Ltd   (South Korea)

Author keywords

Electrical electronic; Electrochemistry; Plating; Scanning electron microscopy (sem); Three dimensional packaging

Indexed keywords

3-DIMENSIONAL; CHIP STACKING; DEEP REACTIVE ION ETCHING; ELECTRICAL/ELECTRONIC; ELECTROPLATING PROCESS; FILLING RATE; FILLING RATIO; FUNCTIONAL LAYER; PERIODIC PULSE; PULSED CURRENTS; SI CHIPS; SI WAFER; THREE DIMENSIONAL CHIP STACKING; THREE DIMENSIONAL PACKAGING; THROUGH-SILICON-VIA; VIA-WALL; WAVE CURRENT; WAVE FORMS;

CHIP SCALE PACKAGES; ELECTROCHEMISTRY; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTROPLATING; FILLING; REACTIVE ION ETCHING; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING SILICON COMPOUNDS; SILICON OXIDES; SILICON WAFERS;

THREE DIMENSIONAL;

EID: 77955688850     PISSN: 17388228     EISSN: None     Source Type: Journal    
DOI: 10.3365/KJMM.2010.48.07.667     Document Type: Article

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