-
1
-
-
32844465023
-
Genuine technologies for tree-dimensional (3D) LSI
-
Katsuya Okumura and Nobuo Hayasaka: "Genuine Technologies for Tree-Dimensional (3D) LSI" Proc. of SSDM, Nagoya, Japan, September 17-20, 2002, pp. 312-313
-
Proc. of SSDM, Nagoya, Japan, September 17-20, 2002
, pp. 312-313
-
-
Okumura, K.1
Hayasaka, N.2
-
2
-
-
0011926220
-
Superfine flip chip interconnections in 20 μm-pitch
-
Kazumasa Tanida, Yoshihiro Tomita, Tadahiro Morifuji, Tatsuya Ando, Ryoichi Kajiwara, Naotaka Tanaka, Tomotoshi Sato, Kenji Takahashi and Manabu Bonkohara: "Superfine Flip Chip Interconnections in 20 μm-pitch" Proc. of 2002 International Conference on Electronics Packaging (ICEP), Tokyo, Japan, April 17-19, 2002, pp.333-338.
-
Proc. of 2002 International Conference on Electronics Packaging (ICEP), Tokyo, Japan, April 17-19, 2002
, pp. 333-338
-
-
Tanida, K.1
Tomita, Y.2
Morifuji, T.3
Ando, T.4
Kajiwara, R.5
Tanaka, N.6
Sato, T.7
Takahashi, K.8
Bonkohara, M.9
-
3
-
-
0035300622
-
Current status of research and development for three-dimensional chip stack technology
-
Kenji Takahashi, Hiroshi Terao, Yoshihiro Tomita, Yasuhiro Yamaji, Masataka Hoshino, Tomotoshi Sato, Tadahiro Morifuji Masahiro Sunohara and Manabu Bonkohara: "Current Status of Research and Development for Three-Dimensional Chip Stack Technology", Jpn. J. Appl. Phys. Vol.40, pp.3032-3037 (2001)
-
(2001)
Jpn. J. Appl. Phys.
, vol.40
, pp. 3032-3037
-
-
Takahashi, K.1
Terao, H.2
Tomita, Y.3
Yamaji, Y.4
Hoshino, M.5
Sato, T.6
Morifuji, T.7
Sunohara, M.8
Bonkohara, M.9
-
4
-
-
0038355685
-
Research for conductive interconnections through silicon substrates
-
Takashi Takizawa, Satoshi Yamamoto, Kazuhisa Itoi, Hironari Nakamura and Tatsuo Suemasu: "Research for Conductive Interconnections through Silicon Substrates" Proc. of The Seventh International Micromachine Symposium, Tokyo, Japan, October 31-November1, 2001, pp.181-186
-
Proc. of the Seventh International Micromachine Symposium, Tokyo, Japan, October 31-November1, 2001
, pp. 181-186
-
-
Takizawa, T.1
Yamamoto, S.2
Itoi, K.3
Nakamura, H.4
Suemasu, T.5
-
5
-
-
0036120704
-
Conductive interconnections through thick substrates for 3D packaging
-
Takashi Takizawa, Satoshi Yamamoto, Kazuhisa Itoi and Tatsuo Suemasu: "Conductive Interconnections through Thick Substrates for 3D Packaging" Proc. of The Fifteenth IEEE International Conference on Micro Electro Mechanical Systems, Las Vegas, Nevada, USA, January 20-24, 2002, pp.388-391
-
Proc. of the Fifteenth IEEE International Conference on Micro Electro Mechanical Systems, Las Vegas, Nevada, USA, January 20-24, 2002
, pp. 388-391
-
-
Takizawa, T.1
Yamamoto, S.2
Itoi, K.3
Suemasu, T.4
-
6
-
-
0038355681
-
High aspect ratio copper via fill used for three dimensional chip stacking
-
Kazuo Kondo, Takuji Okamura, Jian Jun Sun, Manabu Tomisaka, Hitoshi Yonemura, Masataka Hoshino and Kenji Takahashi: "High Aspect Ratio Copper Via Fill used for Three Dimensional Chip Stacking" Proc. of 2002 International Conference on Electronics Packaging (ICEP), Tokyo, Japan, April 17-19, 2002, pp.327-332
-
Proc. of 2002 International Conference on Electronics Packaging (ICEP), Tokyo, Japan, April 17-19, 2002
, pp. 327-332
-
-
Kondo, K.1
Okamura, T.2
Sun, J.J.3
Tomisaka, M.4
Yonemura, H.5
Hoshino, M.6
Takahashi, K.7
-
7
-
-
0035016478
-
High density electrical feedthrough fabricated by deep reactive ion etching of pyrex glass
-
Xinghua Li, Takashi Abe, Yongxun Liu and Masayoshi Esashi: "High Density Electrical Feedthrough Fabricated by Deep Reactive Ion Etching of Pyrex Glass" Proc. of The Fourteenth IEEE International Conference on Micro Electro Mechanical Systems, Interlaken, Switzerland, January 21-25, 2001, pp. 98-101
-
Proc. of the Fourteenth IEEE International Conference on Micro Electro Mechanical Systems, Interlaken, Switzerland, January 21-25, 2001
, pp. 98-101
-
-
Li, X.1
Abe, T.2
Liu, Y.3
Esashi, M.4
-
8
-
-
0038694061
-
Interconnection through-holes filled with conductive paste in silicon substrates using vacuum printing method
-
Hironari Nakamura, Satoshi Yamamoto, Tatsuo Suemasu, Takashi Takizawa and Kenji Kanbara: "Interconnection Through-Holes Filled With Conductive Paste In Silicon Substrates Using Vacuum Printing Method" Proc. of the 16th JIEP
-
Proc. of the 16th JIEP
-
-
Nakamura, H.1
Yamamoto, S.2
Suemasu, T.3
Takizawa, T.4
Kanbara, K.5
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