Current status of research and development for three-dimensional chip stack technology

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 40, Issue 4 B, 2001, Pages 3032-3037

  Takahashi, Kenji ^a   Terao, Hiroshi ^a   Tomita, Yoshihiro ^a   Yamaji, Yasuhiro ^a   Hoshino, Masataka ^a   Sato, Tomotoshi ^a   Morifuji, Tadahiro ^a   Sunohara, Masahiro ^a   Bonkohara, Manabu ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

Electronic system integration; Flip chip bonding; Thermal management; Three dimensional packaging; Through via; Underfill; Wafer thinning

Indexed keywords

FLIP CHIP DEVICES; LSI CIRCUITS; OPTOELECTRONIC DEVICES; RESEARCH AND DEVELOPMENT MANAGEMENT; WSI CIRCUITS;

THREE DIMENSIONAL CHIP STACK TECHNOLOGY; WAFER THINNING;

CHIP SCALE PACKAGES;

EID: 0035300622     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.40.3032     Document Type: Article

References (7)