Via-filling using electroplating for build-up PCBs

Electrochimica Acta

Volumn 47, Issue 1, 2001, Pages 85-89

  Kobayashi, Takeshi ^a,b   Kawasaki, Junichi ^a   Mihara, Kuniaki ^a   Honma, Hideo ^a,b  

^a KANTO GAKUIN UNIVERSITY   (Japan)

^b Research and Development Center   (Japan)

Author keywords

Build up PCB; Electroplating; Filling; Micro via

Indexed keywords

COPPER COMPOUNDS; ELECTRONICS PACKAGING; MULTILAYERS; PRINTED CIRCUIT MANUFACTURE;

COPPER SULFATE;

ELECTROPLATING;

EID: 0035450610     PISSN: 00134686     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0013-4686(01)00592-8     Document Type: Article

References (4)

1. Y. Tsukada, J. Jpn. Inst. Electron. Pack. 11 (5) (1996) 306.
2. D. Schattka, S. Winkels, J.W. Schultze, Metalloberfläche 51 (1997) 823.
3. S. Honda, J. Jpn. Inst. Electron. Pack. 11 (7) (1996) 462.
4. S. Nakatani, S. Nakamura, A. Wada, The 9th National Convention Record JIPC, 1995, p. 57.