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2009 International Conference on Electronic Packaging Technology and High Density Packaging, ICEPT-HDP 2009

Volumn , Issue , 2009, Pages 23-27

Parametric study of electroplating-based via-filling process for TSV applications

(5) Tsui, K Y K a Yau, S K a Leung, V C K a Sun, P a Shi, D X Q a

a HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER LAYERS; CHIP SIZES; DEEP REACTIVE ION ETCHING; ELECTROPLATING PROCESS; INFLUENCE FACTORS; KEY FACTORS; KEY PARAMETERS; KEY PROCESS; PARAMETRIC STUDY; POWER WAVEFORMS; PROCESS PARAMETERS; SEED LAYER; SPUTTERING PROCESS; THROUGH-SILICON-VIA; VIA FILLING; VOID-FREE; VOLTAGE WAVEFORMS;

CHIP SCALE PACKAGES; ELECTROPLATING; FILLING; PACKAGING; PLASMA DEPOSITION; REACTIVE ION ETCHING; SEMICONDUCTING SILICON COMPOUNDS; SILICON OXIDES; SILICON WAFERS;

PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION;

EID: 70449781366 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ICEPT.2009.5270801 Document Type: Conference Paper

Times cited : (13)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.