Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

Microelectronic Engineering

Volumn 87, Issue 3, 2010, Pages 470-476

  Gagnard, Xavier ^a   Mourier, Thierry ^b  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

Author keywords

Integration DRIE deposition copper silicon thinning wafer bonding; TSV 3Di aspect ratio via first via last packaging

Indexed keywords

TSV 3DI ASPECT RATIO VIA FIRST VIA LAST PACKAGING; VIA FIRST;

APPROXIMATION THEORY; ASPECT RATIO; CHIP SCALE PACKAGES; COST REDUCTION; DIGITAL CAMERAS; DIGITAL IMAGE STORAGE; ELECTRIC NETWORK ANALYSIS; FAILURE ANALYSIS; IMAGE SENSORS; INTEGRATED CIRCUITS; INTEGRATION; PACKAGING; PRESSURE DROP; QUALITY ASSURANCE; SAFETY FACTOR; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TECHNOLOGICAL FORECASTING; TECHNOLOGY; WAFER BONDING;

THREE DIMENSIONAL;

EID: 74649084370     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.05.035     Document Type: Article

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