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Volumn 87, Issue 2, 2010, Pages 208-215

Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits

Author keywords

3D ICs; Durability; Finite element; Through silicon vias

Indexed keywords

3-DIMENSIONAL; 3D ICS; ACCELERATED THERMAL CYCLES; ACTIVE LAYER; ANALYTICAL APPROACH; COFFIN-MANSON; CONTINUUM DAMAGE MODEL; COPPER INTERCONNECTS; DESIGN PARAMETERS; DIRECT CHIP ATTACH; FATIGUE LIFE; FINITE ELEMENT; GENERAL LINEAR MODEL ANALYSIS; IC PACKAGE; IC PACKAGING; INFLUENTIAL FACTORS; INTERLAYER BONDING; ISOTROPIC HARDENINGS; MINITAB; NON-LINEAR RESPONSE; NUMBER OF CYCLES TO FAILURE; NUMERICAL EXPERIMENTS; OPTIMIZING DESIGN; OPTIMUM DESIGNS; ORTHOGONAL ARRAY; PLASTIC MATERIALS; SILICON LAYER; SOLDER INTERCONNECTS; SOLDER JOINTS; THERMO-MECHANICAL DURABILITY; THERMOMECHANICAL RELIABILITY; THREE DIMENSIONAL INTEGRATED CIRCUITS; THROUGH SILICON VIAS; THROUGH-SILICON-VIA; UNDERFILL PROPERTIES; UNDERFILLS;

EID: 70450233523     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.07.022     Document Type: Article
Times cited : (92)

References (18)
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    • P.S. Andry, C. Tsang, E. Sprogie, C. Patel, S.L. Wright, B.C. Webb, L.P. Buchwalter, D. Manzer, R. Horton, R. Polastre, J. Knickerbocker, CMOS-compatible process for fabricating electrical through silicon vias, RC23867 (W0602-049) February 3rd, 2006, Electrical Engineering.
    • P.S. Andry, C. Tsang, E. Sprogie, C. Patel, S.L. Wright, B.C. Webb, L.P. Buchwalter, D. Manzer, R. Horton, R. Polastre, J. Knickerbocker, CMOS-compatible process for fabricating electrical through silicon vias, RC23867 (W0602-049) February 3rd, 2006, Electrical Engineering.
  • 15
    • 0003938530 scopus 로고
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.